数字家庭——传输与存储篇电力线传输与储存科技加持数位家庭逐渐成型

经过2004年的激情讨论后,表面上"数字家庭"这个名词似乎再也激不起产业界及分析师等权威人士的热情.然而情况却不然,随着网络的发展、生活习惯的改变及厂商推出的产品来观察,"数字家庭"这个名词正逐步转为动词,经过多年的酝酿,"数位家庭"终于逐渐成型.     

探询中国3G决策思维

2003年以后,全球3G市场进入新的阶段.跨国通信巨头们纷纷宣称,已经在WCDMA、cdma 2000两大标准方面取得了实质性进展,全面支持商用化.同时,集中开发WCDMA设备的欧洲厂商对于中国提出的TD-SCDMA也张开了怀抱,关于两大标准互补性的言论不绝于耳.香港和黄电讯在欧洲几国全面建设和运营3 G网络,中国的近邻日本、韩国3 G市场开始出现快速增长的迹象.这些经历无法代替一个关键性的角色,世界最大通信市场所在地的中国尚未吹响3G的号角.     

多名学者欲联名状告超星侵权网络盗版顽疾再刺业界神经

接连而至的官司,再次搅起版权领域的千层浪! 2007年4月17日,中国社科院研究员吴锐及其导师刘宝才的一纸诉状,将数字图书馆解决方案提供商北京世纪超星公司(下称"超星")推上了北京海淀区法院的被告席.     

告阿里巴巴商标侵权?这个玩笑开得太大了

一家国内最大的电子商务公司的商标被一家名不见经传的企业所拥有,听起来似乎很荒唐,然而细细深究,却更像是一个拙劣的玩笑. 11月6日,阿里巴巴网络有限公司(股份代号:1688)于香港联合交易所有限公司主板开始交易.开盘即达到30港元,较发行价13.5港元上涨122%,加上超额认购部分,融资17亿美元,市值超过200亿美元,创下中国互联网市值之最,同时也是全球最大互联网融资.     

iSCSI分析及其Linux驱动实现

iSCSI,是IETF制订的用于将SCSI数据块映射成以太网数据包的一项标准,是实现IP存储的重要技术之一。本文分析了iSCSI协议及其Linux系统中驱动的实现方法。     

IMS:在不断质疑中前进

IMS的出现为下一代网络的发展和业务的融合提供了一种思路和方式,但IMS本身依然还不是十分成熟,还存在着一些问题,如理解和评估困难、标准和产品脱节、商业模式不明确等,业界也有不同的声音.但尽管如此,IMS还是在一步步变成现实,这表现在标准化和运营商的网络部署和互操作性方面.     

IEC TC47半导体器件标准化最新动态

1 IEC TC47年会召开 2007年11月5～9日,在法国图卢兹召开了IEC TC47、SC47A、SC47E及相关工作组会议,来自英国、美国、德国、日本、韩国和中国国家委员会的数十名代表参加了会议.     

周忆,走向国际舞台的公关丽人

2007年3月9日,周五,晚.位于北京王府井大街旁的金宝大厦小南国餐厅内一派喜庆.50多位中国主流的IT媒体总编辑们相聚在这里,他们是来祝贺周忆女士荣升IBM亚太区副总裁的.这个职务在历史上(包括IBM在内的所有跨国公司),从来没有降临到任何亚裔人士的头上.周忆的进步,表明了中国本土公关人才开始走向国际舞台.     

支持多个SD卡的切换解决方案

市面上许多手机和便携设备(如数码相机)都能通过插入一块标准、小型或微型SD卡来增加内存.这一功能刺激了共享或扩展主机处理器SDIO(安全数字I,0)端口从而连接多个设备的需求.SD卡接口设计为一个6通道总线,其中1个通道用于时钟、一个用于命令,其余4个用于数据线路.     

得胜：从广东制造走向世界品牌——专访广东得胜电子有限公司总经理杨志豪

在第十七届中国国际专业音响、灯光、乐器及技术展览会的五号馆,有一个布置精致、宽敞明亮的展台,这就是著名的广东得胜电子有限公司展台.展区的外面,是得胜公司推出的"集成应用"系统方案的宣传画.进入展区,整洁的展台上按产品类别展示着得胜牌传声器、耳机、扩音器及科声产品.透明的玻璃演出间,乐队正在里面投入地演奏.展区中得胜公司的工作人员正在接待来参观的客人.     

FFT algorithms for prime transform sizes and their implementationson VAX, IBM3090VF, and IBM RS/6000

Variants of the Winograd fast Fourier transform (FFT) algorithm for prime transform size that offer options as to operational counts and arithmetic balance are derived. Their implementations on VAX, IBM 3090 VF, and IBM RS/6000 are discussed. For processors that perform floating-point addition, floating-point multiplication, and floating-point multiply-add with the same time delay, variants of the FFT algorithm have been designed such that all floating-point multiplications can be overlapped by using multiply-add. The use of a tensor product formulation, throughout, gives a means for producing variants of algorithms matching computer architectures     

Comments on “Leading-zero anticipatory logic for high-speedfloating point addition” [with reply]

For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. However, I found the LZ counter circuit shown in the paper similar to the LZ counter circuit that I have published previously in the period from 1992-94     

Approaching a machine-application bound in delivered performance onscientific code

A performance bounding methodology that explains the performance of loop-dominated scientific applications on particular systems is presented. The throughput of key hardware units that are common bottlenecks in concurrent machines is modeled. A workload characterization is proposed, and upper bounds on the performance of specific machine-workload pairs are derived. Comparing delivered performance with bounds focuses attention on areas for improvement and indicates how much improvement might be attainable. A detailed analysis and performance improvement effort for the IBM RS/6000 produced an average lower bound of 1.27 clocks per floating-point operation (CPF), whereas machine peak performance is 0.5 CPF and the V2.01 Fortran compiler attains only 2.43 CPF. Code improvements in this study have achieved 1.36 CPF, increasing the harmonic mean steady-state inner loop performance to 97.6% of the MFLOPS bound. Subsequently, the V2.02 compiler achieved 1.75 CPF, and 1.60 with carefully chosen preprocessing     

Protocol architecture for multimedia applications over ATM networks

At the data-link layer, ATM offers a number of features, such as high-bandwidth and per-session quality-of-service (QoS) guarantees, making it particularly attractive to multimedia applications. Unfortunately, many of these features are not visible to applications because of the inadequacies of existing higher-level protocol architectures. Although there is considerable effort underway to tune these protocols for ATM networks, we believe that a new ATM-specific protocol stack is essential to effectively exploit all the benefits of ATM. We describe the semantics of such a protocol stack, and discuss its advantages over traditional protocol architectures from the perspective of multimedia applications. The performance impact of the new protocol architecture is experimentally demonstrated on a video conferencing testbed built around IBM RS/6000's equipped with prototype hardware for video/audio processing, and connected via ATM links     

计算机串行通信综述

本文着重向读者介绍目前流行的几种计算机串行通信规程，它们是ＥＩＡ－ＲＳ－２３２Ｃ、ＥＩＡ－ＲＳ－４２２Ａ、ＥＩＡ－ＲＳ－４２３Ａ、ＥＩＡ－ＲＳ－４４９、ＥＩＡ－ＲＳ－４８５、ＡＲ－ＩＮＣ－４２９等。     

RS码译码器综述

ＲＳ码是差错控制领域中一类重要的线性分组码，由于具有很强的纠随机错和突发错的能力，被广泛应用于各种差错控制系统中，本文从ＲＳ译码算法，ＲＳ译码器的ＶＬＳＩ结构和ＲＳ码系统性能三方面论述了ＲＳ译码器的发展现状，并展望了译码器的未来发展方向。     

变参数RS译码器IP核的实现

设计出一种码长可以变化的RS码译码器IP核电路,可进行RS(15,5)、RS(15,7)、RS(15,9)以及RS(15,11)的译码。译码器电路使用BM迭代译码算法,并在硬件电路中加以改进,使得电路能扩充到编译纠错位数多的复杂RS码。该译码器电路尽可能多地使用可以共享的模块,降低了电路的规模。硬件电路采用V erilogHDL进行描述,并在FPGA上进行了验证,同时给出了硬件电路在逻辑分析仪上得到的结果。     

基于FPGA的RS译码器的设计与实现

针对Reed-Solomon（RS）码译码过程复杂、译码速度慢和专用译码器价格高等问题,以联合信息分发系统终端J系列报文信息位采用的RS（31,15）码为例,介绍了基于改进的无求逆运算的Berlekamp-Massey（BM）迭代算法的RS译码原理,采用Verilog硬件描述语言对译码器中各个子模块进行了设计,并基于现场可编程门阵列平台,在QuartusII6.0环境下进行了仿真,验证了RS译码器的纠错能力,实现了参数化与模块化的RS译码器设计。     

数字视频广播卫星传送标准中的RS码

在数字卫星电视信号传送中的ＦＥＣ中,常采用ＲＳ码,讨论了ＲＳ码的三个问题;１）伽罗华域ＧＦ（２＾８）;２）ＲＳ的码的编码;３）ＲＳ码的检错和纠错。     

Filterbank Decompositions for (Non)-Systematic Reed–Solomon Codes With Applications to Soft Decoding

This paper focuses on Reed-Solomon (RS) codes, which are the most widespread classical error correcting codes. Recently, we have shown that an finite-impulse response (FIR) critically subsampled filterbank representation can be derived for some RS codes. However, this work only addresses RS codes with a non-coprime codeword and dataword length, seriously limiting its practical usability. In this paper, an alternative purely algebraic method is presented to construct such a filterbank. Apart from providing additional insight into the algebraic structure of (non-systematic) RS codes, this method is suited to eliminate the non-coprimeness constraint mentioned before. Using this filterbank decomposition, a RS code is broken into smaller subcodes that can subsequently be used to build a soft-in soft-out (SISO) RS decoder. It is shown how any RS code, written as an FIR filterbank, can be SISO decoded using the filterbank based decoder. Owing to the importance of systematic RS codes, it is shown that any systematic RS code can be decoded using the FIR filterbank decomposition. This leads to better decoding performance in addition with a slightly lower complexity. A further extension towards systematic RS codes is also presented in this paper resulting in an infinite-impulse response critically subsampled filterbank representation.