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1.
Y. P. Chen J. P. Faurie S. Sivananthan G. C. Hua N. Otsuka 《Journal of Electronic Materials》1995,24(5):475-481
CdTe(lll)B layers have been grown on misoriented Si(001). Twin formation inside CdTe(lll)B layer is very sensitive to the
substrate tilt direction. When Si(001) is tilted toward [110] or [100], a fully twinned layer is obtained. When Si(001) is
tilted toward a direction significantly away from [110], a twin-free layer is obtained. Microtwins inside the CdTe(111)B layers
are overwhelmingly dominated by the lamellar twins. CdTe(111)B layers always start with heavily lamellar twinning. For twin-free
layers, the lamellar twins are gradually suppressed and give way to twin-free CdTe(111)B layer. The major driving forces for
suppressing the lamellar twinning are the preferential orientation of CdTe[11-2] along Si[1-10] and lattice relaxation. Such
preferential orientation is found to exist for the CdTe(111)B layers grown on Si(001) tilted toward a direction between [110]
and [100]. 相似文献
2.
H. Ebe T. Okamoto H. Nishino T. Saito Y. Nishijima M. Uchikoshi M. Nagashima H. Wada 《Journal of Electronic Materials》1996,25(8):1358-1361
CdTe epilayers were grown directly on (100), (211), and (111) silicon substrates by metalorganic chemical vapor deposition
(MOCVD). The crystallinity and the growth orientation of the CdTe film were dependent on the surface treatment of the Si substrate.
The surface treatment consisted of exposure of the Si surface to diethyltelluride (DETe) at temperatures over 600°C prior
to CdTe growth. Direct growth of CdTe on (100) Si produced polycrystalline films whereas (lll)B single crystals grew when
Si was exposed to DETe prior to CdTe growth. On (211) Si, single crystal films with (133)A orientation was obtained when grown
directly; but produced films with (211)A orientation when the Si surface was exposed to DETe. On the other hand, only (lll)A
CdTe films were possible on (111) Si, both with and without Te source exposure, although twinning was increased after exposure.
The results indicate that the exposure to a Te-source changes the initial growth stage significantly, except for the growth
on (111) Si. We propose a model in which a Te atom replaces a Si atom that is bound to two Si atoms. 相似文献
3.
S. R. Rao S. S. Shintri J. K. Markunas R. N. Jacobs I. B. Bhat 《Journal of Electronic Materials》2011,40(8):1790-1794
High-quality (211)B CdTe buffer layers are required during Hg1−x
Cd
x
Te heteroepitaxy on Si substrates. In this study, direct metalorganic vapor-phase epitaxy (MOVPE) of (211)B CdTe on Si, as
well as CdTe on Si using intermediate Ge and ZnTe layers, has been achieved. Tertiary butyl arsine was used as a precursor
to enable As surfactant action during CdTe MOVPE on Si. The grown CdTe/Si films display a best x-ray diffraction rocking-curve
full-width at half-maximum of 64 arc-s and a best Everson etch pit density of 3 × 105 cm−2. These values are the best reported for MOVPE-grown (211)B CdTe/Si and match state-of-the-art material grown using molecular-beam
epitaxy. 相似文献
4.
S. R. Rao S. S. Shintri J. K. Markunas R. N. Jacobs I. B. Bhat 《Journal of Electronic Materials》2010,39(7):996-1000
High-quality (211)B CdTe buffer layers on Si substrates are required to enable Hg1–x
Cd
x
Te growth and device fabrication on lattice-mismatched Si substrates. Metalorganic vapor-phase epitaxy (MOVPE) of (211)B CdTe
on Si substrates using Ge and ZnTe interlayers has been achieved. Cyclic annealing has been used during growth of thick CdTe
layers in order to improve crystal quality. The best (211)B CdTe/Si films grown in this study display a low x-ray diffraction
(XRD) rocking-curve full-width at half-maximum (FWHM) of 85 arcsec and etch pit density (EPD) of 2 × 106 cm−2. These values are the best reported for MOVPE-grown (211) CdTe/Si and are comparable to those for state-of-the-art molecular
beam epitaxy (MBE)-grown CdTe/Si. 相似文献
5.
W. F. ZHAO R. N. JACOBS M. JAIME-VASQUEZ L. O. BUBULAC DAVID J. SMITH 《Journal of Electronic Materials》2011,40(8):1733-1737
Transmission electron microscopy and small-probe microanalysis have been used to investigate the microstructure and compositional
profiles of CdTe(211)B/ZnTe/Si(211) heterostructures. Thin ZnTe buffer layers and subsequent thick CdTe layers were grown
on Si(211) substrates using molecular beam epitaxy. Many {111}-type stacking faults were found to be present throughout the
entire ZnTe layer, terminating near the point of initiation of CdTe growth. A rotation angle of about 3.5° was observed between
lattice planes of the Si substrate and the final CdTe epilayer. Local lattice parameter measurement and elemental profiles
indicated that some intermixing of Zn and Cd had taken place. The average widths of the ZnTe layer and the (Cd,Zn)Te transition
region were found to be roughly 6.5 nm and 3.5 nm, respectively. 相似文献
6.
Heteroepitaxy of HgCdTe(112) infrared detector structures on Si(112) substrates by molecular-beam epitaxy 总被引:4,自引:0,他引:4
T. J. De Lyon R. D. Rajavel J. E. Jensen O. K. Wu S. M. Johnson C. A. Cockrum G. M. Venzor 《Journal of Electronic Materials》1996,25(8):1341-1346
High-quality, single-crystal epitaxial films of CdTe(112)B and HgCdTe(112)B have been grown directly on Si(112) substrates
without the need for GaAs interfacial layers. The CdTe and HgCdTe films have been characterized with optical microscopy, x-ray
diffraction, wet chemical defect etching, and secondary ion mass spectrometry. HgCdTe/Si infrared detectors have also been
fabricated and tested. The CdTe(112)B films are highly specular, twin-free, and have x-ray rocking curves as narrow as 72
arc-sec and near-surface etch pit density (EPD) of 2 × 106 cm−2 for 8 μm thick films. HgCdTe(112)B films deposited on Si substrates have x-ray rocking curve FWHM as low as 76 arc-sec and
EPD of 3-22 × 106 cm−2. These MBE-grown epitaxial structures have been used to fabricate the first high-performance HgCdTe IR detectors grown directly
on Si without use of an intermediate GaAs buffer layer. HgCdTe/Si infrared detectors have been fabricated with 40% quantum
efficiency and R0A = 1.64 × 104 Ωm2 (0 FOV) for devices with 7.8 μm cutoff wavelength at 78Kto demonstrate the capability of MBE for growth of large-area HgCdTe
arrays on Si. 相似文献
7.
Microstructural and optical characterization of CdTe(211)B/ZnTe/Si(211) grown by molecular beam epitaxy 总被引:2,自引:0,他引:2
S. Rujirawat David J. Smith J. P. Faurie G. Neu V. Nathan S. Sivananthan 《Journal of Electronic Materials》1998,27(9):1047-1052
CdTe layers have been grown by molecular beam epitaxy on 3 inch nominal Si(211) under various conditions to study the effect
of growth parameters on the structural quality. The microstructure of several samples was investigated by high resolution
transmission electron microscopy (HRTEM). The orientation of the CdTe layers was affected strongly by the ZnTe buffer deposition
temperature. Both single domain CdTe(133)B and CdTe(211)B were obtained by selective growth of ZnTe buffer layers at different
temperatures. We demonstrated that thin ZnTe buffer layers (<2 nm) are sufficient to maintain the (211) orientation. CdTe
deposited at ∼300°C grows with its normal lattice parameter from the onset of growth, demonstrating the effective strain accommodation
of the buffer layer. The low tilt angle (<1°) between CdTe[211] and Si[211] indicates that high miscut Si(211) substrates
are unnecessary. From low temperature photoluminescence, it is shown that Cd-substituted Li is the main residual impurity
in the CdTe layer. In addition, deep emission bands are attributed to the presence of AsTe and AgCd acceptors. There is no evidence that copper plays a role in the impurity contamination of the samples. 相似文献
8.
R. Sporken D. Grajewski Y. Xin F. Wiame G. Brill P. Boieriu A. Prociuk S. Rujirawat N. K. Dhar S. Sivananthan 《Journal of Electronic Materials》2000,29(6):760-764
CdTe
B was grown on As-terminated Si(111) by molecular beam epitaxy (MBE). Nucleation and interface properties were studied by
photoelectron spectroscopy, scanning tunneling microscopy, electron diffraction, and energy-dispersive spectroscopy of x-rays.
Selective growth on Si(111) was investigated either by using SiO2 as a mask, or by growing on a patterned CdTe seed layer. The highest temperature where CdTe nucleates on As-terminated Si(111)
surfaces is typically in the range of 220–250°C. On a SiO2 mask, CdTe nucleates at the same temperatures, leading to polycrystalline growth. However, homoepitaxy of CdTe is possible
around 300°C. Hence, CdTe can be grown selectively on a patterned CdTe seed layer on Si(111). This is confirmed by scanning
electron microscopy and scanning Auger microscopy. 相似文献
9.
10.
L. A. Almeida Y. P. Chen J. P. Faurie S. Sivananthan David J. Smith S. -C. Y. Tsen 《Journal of Electronic Materials》1996,25(8):1402-1405
We have systematically studied the growth of CdTe (lll)B on Si(001)with different atomic step structures, defined uniquely
by miscut tilt angle and direction. X-ray double crystal rocking curve (DCRC) analysis has been used to evaluate the crystalline
quality and twin content of the films. High-resolution electron microscopy has been used to examine the CdTe(lll)B/Si(001)
interface and to follow the microstructural evolution as a function of distance from the interface. Our results show that
the formation of double domains and twins is very sensitive to the tilt parameters. When growth conditions are optimized,
twins are not observed at distances greater than about 2.5 microns from the substrate surface. The best quality films exhibit
a DCRC FWHM of 60 arc sec, for a film thickness of 17 μm, the lowest value ever reported for heteroepitaxial growth of CdTe
on Si or GaAs. In efforts to improve the nucleation process, precursors such as Te and As have been used, and we have shown
that they improve the stability of the heterointerface. 相似文献
11.
M. Carmody A. Yulius D. Edwall D. Lee E. Piquette R. Jacobs D. Benson A. Stoltz J. Markunas A. Almeida J. Arias 《Journal of Electronic Materials》2012,41(10):2719-2724
Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤106?cm?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality. 相似文献
12.
J.D. Benson L.A. Almeida M.W. Carmody D.D. Edwall J.K. Markunas R.N. Jacobs M. Martinka U. Lee 《Journal of Electronic Materials》2007,36(8):949-957
The as-grown molecular beam epitaxy (MBE) (211)B HgCdTe surface has variable surface topography, which is primarily dependent on substrate temperature and substrate/epilayer mismatch. Nano-ripple formation and cross-hatch patterning are the predominant structural features observed. Nano-ripples preferentially form parallel to the \( [\bar {1}11] \) and are from 0 Å to 100 Å in height with a wavelength between 0.1 μm and 0.8 μm. Cross-hatch patterns result from slip dislocations in the three {111} planes intersecting the (211) growth surface. The cross-hatch step height is 4 ± 1 Å (limited data set). This indicates that only a bi-layer slip (Hg/Cd + Te) in the {111} slip plane occurs. For the deposition of MBE (211)B HgCdTe/CdTe/Si, the reorientation of multiple nano-ripples coalesced into “packets” forms cross-hatch patterns. The as-grown MBE (211)B CdTe/Si surface is highly variable but displays nano-ripples and no cross-hatch pattern. Three types of defects were observed by atomic force microscopy (AFM): needle, void/hillock, and voids. 相似文献
13.
Kwang-Chon Kim Seung Hyub Baek Hyun Jae Kim Jin Dong Song Jin-Sang Kim 《Journal of Electronic Materials》2012,41(10):2795-2798
Epitaxial CdTe thin films were grown on GaAs/Si(001) substrates by metalorganic chemical vapor deposition using thin GaAs as a buffer layer. The interfaces were investigated using high-resolution transmission electron microscopy and geometric phase analysis strain mapping. It was observed that dislocation cores exist at the CdTe/GaAs interface with periodic distribution. The spacing of the misfit dislocation was measured to be about 2?nm, corresponding to the calculated spacing of a misfit dislocation (2.6?nm) in CdTe/Si with Burgers vector of a[110]/2. From these results, it is suggested that the GaAs buffer layer effectively absorbs the strain originating from the large lattice mismatch between the CdTe thin film and Si substrate with the formation of periodic structural defects. 相似文献
14.
H. Nishino S. Murakami T. Saito Y. Nishijima H. Takigawa 《Journal of Electronic Materials》1995,24(5):533-537
We studied dislocation etch pit density (EPD) profiles in HgCdTe(lOO) layers grown on GaAs(lOO) by metalorganic chemical vapor
deposition. Dislocation profiles in HgCdTe(lll)B and HgCdTe(lOO) layers differ as follows: Misfit dislocations in HgCdTe(lll)B
layers are concentrated near the HgCdTe/CdTe interfaces because of slip planes parallel to the interfaces. Away from the HgCdTe/CdTe
interface, the HgCdTe(111)B dislocation density remains almost constant. In HgCdTe(lOO) layers, however, the dislocations
propagate monotonically to the surface and the dislocation density decreases gradually as dislocations are incorporated with
increasing HgCdTe(lOO) layer thicknesses. The dislocation reduction was small in HgCdTe(lOO) layers more than 10 μm from the
HgCdTe/CdTe interface. The CdTe(lOO) buffer thickness and dislocation density were similarly related. Since dislocations glide
to accommodate the lattice distortion and this movement increases the probability of dislocation incorporation, incorporation
proceeds in limited regions from each interface where the lattice distortion and strain are sufficient. We obtained the minimum
EPD in HgCdTe(100) of 1 to 3 x 106 cm-2 by growing both the epitaxial layers more than 8 μm thick. 相似文献
15.
Kwang-Chon Kim Hyun Jae Kim Sang-Hee Suh M. Carmody S. Sivananthan Jin-Sang Kim 《Journal of Electronic Materials》2010,39(7):863-867
Single-crystalline CdTe(133) films have been grown by metalorganic chemical vapor deposition on Si(211) substrates. We studied
the effect of various growth parameters on the surface morphology and structural quality of CdTe films. Proper oxide removal
from the Si substrate is considered to be the principal factor that influences both the morphology and epitaxial quality of
the CdTe films. In order to obtain single-crystalline CdTe(133) films, a two-stage growth method was used, i.e., a low-temperature
buffer layer step and a high- temperature growth step. Even when the low-temperature buffer layer shows polycrystalline structure,
the overgrown layer shows single-crystalline structure. During the subsequent high-temperature growth, two-dimensional crystallites
grow faster than other, randomly distributed crystallites in the buffer layer. This is because the capturing of adatoms by
steps occurs more easily due to increased adatom mobility. From the viewpoint of crystallographic orientation, it is assumed
that the surface structure of Si(211) consists of (111) terrace and (100) step planes with an interplanar angle of 54.8°.
This surface structure may provide many preferable nucleation sites for adatoms compared with nominally flat Si(100) or (111)
surfaces. The surface morphology of the resulting films shows macroscopic rectangular-shaped terrace—step structures that
are considered to be a (111) terrace with two {112} step planes directed toward 〈110〉. 相似文献
16.
The development of HgCdTe detectors requires high sensitivity, small pixel size, low defect density, long-term thermal-cycling reliability, and large-area substrates. CdTe bulk substrates were initially used for epitaxial growth of HgCdTe films. However, CdTe has a lattice mismatch with long-wavelength infrared (LWIR) and middle-wavelength infrared (MWIR) HgCdTe that results in detrimental dislocation densities above mid-106 cm?2. This work explores the use of CdTe/Si as a possible substrate for HgCdTe detectors. Although there is a 19% lattice mismatch between CdTe and Si, the nanoheteroepitaxy (NHE) technique makes it possible to grow CdTe on Si substrates with fewer defects at the CdTe/Si interface. In this work, Si(100) was patterned using photolithography and dry etching to create 500-nm to 1-μm pillars. CdTe was selectively deposited on the pillar surfaces using the close-spaced sublimation (CSS) technique. Scanning electron microscopy (SEM) was used to characterize the CdTe selective growth and grain morphology, and transmission electron microscopy (TEM) was used to analyze the structure and quality of the grains. CdTe selectivity was achieved for most of the substrate and source temperatures used in this study. The ability to selectively deposit CdTe on patterned Si(100) substrates without the use of a mask or seed layer has not been observed before using the CSS technique. The results from this study confirm that CSS has the potential to be an effective and low-cost technique for selective nanoheteroepitaxial growth of CdTe films on Si(100) substrates for infrared detector applications. 相似文献
17.
W. J. Hamilton J. A. Vigil W. H. Konkel V. B. Harper S. M. Johnson 《Journal of Electronic Materials》1993,22(8):879-885
Epitaxial layers of CdTe were grown by metalorganic chemical vapor deposition on surfaces of single crystal, {100} GaAs which
had been ground, polished, and etched to a spherically shaped done. This dome-shaped surface allowed the morphological and
structural properties of the epitaxial CdTe layers to be determined for all 360° of azimuth and up to 15° of polar angle from
the [100] axis within a single growth experiment. At two growth temperatures, approximately 275 and 375°C, the results show
distinct twofold rotational symmetry in both morphology and crystal perfection as determined by x-ray rocking curve measurement.
Surface morphology is superior at azimuths near tilts toward the <111>A pole. Four-sided pyramidal hillocks appear at other
azimuths and at 0° tilt; the symmetry of the hillocks diminishes as the tilt increases. The orientations for growth which
simultaneously minimize the surface defects and rocking curve full-width half-maximum appear to be at locations on the surface
where the surface normal is tilted 3–4° toward the <111>A or <111>B, depending on the temperature regime chosen. Epitaxial
layers grown on planar wafers of {100}GaAs tilted toward <111>Ga and <111>As show surface morphology essentially identical
to the dome at these orientations. The surface morphology of CdTe growth on GaAs/Si wafers suggests that these layers are
tilted toward the <111>B. 相似文献
18.
M. Jaime-Vasquez M. Martinka A.J. Stoltz R.N. Jacobs J.D. Benson L.A. Almeida J.K. Markunas 《Journal of Electronic Materials》2008,37(9):1247-1254
Plasma etching of (112)B InSb to prepare this semiconductor for the heteroepitaxy deposition of CdTe and initial studies of
CdTe epilayers grown by molecular beam epitaxy (MBE) on InSb (112)B substrates cleaned with various plasma treatments are
presented. X-ray diffraction rocking curve maps of the MBE CdTe epilayers on 3-inch InSb (112)B substrates have full-width
at half-maxima (FWHM) values in the range of 20 arcsec to 30 arcsec. An etch pit density analysis of the 3-inch CdTe epilayers
reveals a defect density of 1.0 × 107 cm−2 and 7.7 × 105 cm−2 at the center and edge of the wafer, respectively. Evaluation of a standard HgCdTe annealing process suggests that the removal
of the InSb substrate is likely to be needed prior to any postgrowth annealing in Hg overpressure. Finally, we present a low-energy
helium plasma exposure of wet-etched InSb (112)B substrates that provides a uniform epi-ready surface that is nearly stoichiometric,
and free of oxide and residual contaminants. 相似文献
19.
We discuss various possibilities for determining the orientation of CdTe layers grown on (001) GaAs and in particular, determining
the (001) orientation. This growth orientation is characterized by a three dimensional growth mechanism which controls the
growth in the (111) orientation. We show that a thin layer of ZnTe deposited directly on the oxide free GaAs surface can be
used to determine the (001) orientation, eliminate (111) phases and enhance a two dimensional growth of the CdTe layer, resulting
in an improved crystalline quality and a smooth surface morphology. CdTe layers grown in the (111) direction on oxide free
(001) GaAs substrates contain (111) microtwins and an intermixed (001) phase.
This work is a part of a Ph.D. thesis to be submitted to the Weizmann Institute of Science. 相似文献
20.
A. Krost F. Heinrichsdorff F. Schnabel K. Schatke D. Bimberg H. Cerva 《Journal of Electronic Materials》1994,23(2):135-139
The growth of InP by low-pressure metalorganic chemical vapor deposition on vicinal Si(111), misoriented 3° toward [1-10],
is reported. Antiphase domain-free InP is obtained without any preannealing of the Si substrate. Crystallographic, optical,
and electrical properties of the layers are significantly improved as compared to the best reported InP grown on Si(001).
The high structural perfection is demonstrated by a full width at half maximum (FWHM) of 121 arcs for the (111) Bragg reflex
of InP (thickness = 3.4 μm) as obtained by double crystal x-ray diffraction. The low-temperature photoluminescence (PL) efficiency
is 70% of that of homoepitaxially grown InP layers. The FWHM of the near-gap PL peak is only 2.7 meV as compared to 4.5 meV
of the best material grown on Si(001). For the first time, InP:Fe layers with semi-insulating characteristics (ρ > 3 × 107 Ω-cm) have been grown by compensating the low residual background doping using ferrocene. Semi-insulating layers are prerequisite
for any device application at ultrahigh frequencies. 相似文献