Compact CMOS Baluns for the 4–10 GHz Band Applications

In this paper, we proposed two baluns, a compact balun and a compact balun with imbalance compensation; both are implemented using the one-poly six-metal (1P6M) 0.18 μ m CMOS process. Both baluns have good performance from 4 to 10 GHz, and consume less silicon area due to their compact structure. The self-resonant frequency is increased by properly selecting metal layer for each spiral winding. The compact balun has a magnitude imbalance of 1 dB and a phase imbalance of 4.6 degree from 4 to 10 GHz. With the imbalance compensation, the balun has a magnitude imbalance of 0.6 dB and a phase imbalance of 1.1 degree from 4–10 GHz. Much better results have been achieved for the compact balun with our proposed imbalance compensation method. Both baluns can be used to perform both single-ended/differential and differential/single-ended conversions in different configurations.     

Novel miniaturised wideband baluns for MIC and MMIC applications

Very compact novel planar broadband baluns are described. Each balun consists of two Lange couplers. Less than 0.3 dB and 2.5 degrees for the amplitude and phase balances, respectively, have been measured over the 1.0-2.2 GHz bandwidth for a microstrip balun. As compared with other reported baluns, these baluns are simpler, more compact, easier to design, and fabricated on only one side of the substrate. They are thus very attractive for microwave integrated circuit (MIC) and monolithic microwave integrated circuit (MMIC) applications.<>     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

Design of a wideband multi-standard antenna switch for wireless communication devices

A wideband Low Power Single Pole 6-Throw (SP6T) antenna switch has been designed for GSM/DCS/802.11b mobile standards using a newly improved architecture and fabricated using a pseudomorphic depletion mode 0.18 μm HEMT GaAs process. The switch exhibits less than 1 dB insertion loss and isolation performances from up to 53 dB at 0.8 GHz down to 42 dB at 2.5 GHz. The circuit DC power consumption is less than 500 μW in full power transmission condition and makes it suitable for use in mobile terminals like mobile phones or PDAs. The paper presents simulation results validated by experimental measurements on an IC prototype.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.     

Optimum Design of Wideband Compensated and Uncompensated Marchand Baluns With Step Transformers

This paper presents a design approach for wideband compensated and uncompensated Marchand baluns with stepped-impedance transformers. In order to obtain an equal-ripple bandpass response, conventional Chebyshev polynomials are modified to compensate the effect of the transfer function's dc poles. Unlike the available microwave filter design approaches, which usually require redundant elements, this approach leads to an optimum design by using the minimum number of equal length transmission line elements. Based on this design approach, both compensated and uncompensated Marchand baluns are studied. It is found that increasing difficulty arises when implementing a large bandwidth balun using the widely adopted compensated balun structure. Hence, the uncompensated balun structure becomes a better choice. To validate the proposed design approach, an uncompensated balun is designed on a standard two-sided printed circuit board. The measured results indicate that a return loss greater than 20 dB can be observed from 1 to 7.5 GHz. The phase imbalance is less than 4° and the amplitude is less than 0.5 dB from dc to 7.2 GHz.      

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

Analysis and design of wide band Microstrip-line-fed antenna with defected ground structure for Ku band applications

A wide band Microstrip antenna is proposed for Ku band applications with defected ground structure. A circular shape defect is integrated in the ground plane. A novel equivalent circuit model is proposed for Microstrip patch antenna with defected ground structure. Accurate design equations are presented for the wideband Microstrip antenna and theoretical analysis is done for the proposed structure. The proposed antenna has an impedance bandwidth of 56.67% ranging from 9.8 GHz to 17.55 GHz, which covers Ku-band and partially X-band. The antenna shows good radiation characteristics within the entire band, and has a gain ranging from 5 dBi to 12.08 dBi. Minimum isolation between co-polar and cross-polarization level of 20 dB and 15 dB is achieved in H-plane and E-plane respectively. The simulation of the proposed antenna is done on HFSS v.14, and measured results of fabricated antenna are in good agreement with the theoretical and simulated results.     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

Broadband monolithic passive baluns and monolithic double-balancedmixer

The design and fabrication of four broadband monolithic passive baluns including CPW Marchand, multilayer MS Marchand, planar-transformer and broadside-coupled line baluns are presented. Operational frequencies range from 1.5 GHz to 24 GHz. Maximum relative bandwidths in excess of 3:1 are achieved. Simulated performances using full wave electromagnetic analysis are shown to agree with the measured results. Two accurate equivalent circuit models constructed from either electromagnetic simulated or measured S-parameters are developed for the MS Marchand and transformer baluns making the optimization of baluns and circuit design using the baluns much more efficient. The design of monolithic double-balanced diode mixer using two planar-transformer baluns is also presented. Without DC bias, the mixer shows a minimum conversion loss of 6 dB with the RF at 5 GHz and a LO drive of 15 dBm at 4 GHz. The measured input IP₃ of this mixer is better than 15 dBm over the 4 to 5.75 GHz frequency band