一种全差分增益增强型运算放大器的设计

设计了一种用于高速ADC中的全差分运算放大器。该运算放大器由主运放、4个辅助运放和一种改进型开关电容共模反馈电路组成,主运放采用折叠式共源共栅结构,并引入增益增强技术提高增益。采用SMIC 0.18μm,1.8 V工艺,在Cadence电路设计平台中利用Spectre仿真,结果表明：运放增益达到115 dB,单位增益带宽805 MHz,而功耗仅为10.5 mW,运放在8 ns的时间内可以达到0.01%的建立精度,可用于高速高精度流水线( Pipelined) ADC中。     

一种全差分增益提升运放的设计与建立特性优化

在2．5V电源电压下采用中芯国际（SMIC）0．25μm混合信号CMOS工艺设计了一个单级全差分运算放大器。所设计的运放采用了增益提升技术，其主运放为一个带有开关电容共模反馈的全差分折叠一共源共栅运放。两个带有连续时间共模反馈的全差分折叠一共源共栅运放作为辅运放用来提升主运放的开环增益。此外，本文还提出了一种可用于增益提升运放高速设计的基于仿真的优化方法。仿真结果表明，所设计运放的直流增益可达102dB，单位增益频率为822MHz，通过高速优化，其达到0．1％精度的建立时间为4ns。     

一种采用增益增强技术的全差分运放设计和实现

设计了一种采用增益增强技术并带有共模反馈的全差分运算放大器.该运算放大器主要由三个折叠式共源共栅结构的运放、一个偏置电路和一个共模反馈电路组成.运算放大器采用chartered 0.35 μm CMOS工艺实现,仿真结果表明运放开环增益为106.8 dB,单位增益带宽为58 MHz,相位裕度为79°(负载Cload=1 pF).对流片运放进行测试和分析,运算放大器测试指标和仿真指标基本接近,较好达到预先的设计要求.     

一种高增益全差分运算放大器的分析与设计

采用增益提高技术,设计了一种高增益全差分运算放大器,其主运放和两个辅助运放均为全差分折叠式共源共栅结构,并带有连续时间共模反馈电路。详细地分析了由增益增强结构为此运放带来的零极点对。该运算放大器采用TSMC 0.18 μm CMOS工艺设计,开环直流增益可达138 dB,单位增益带宽为252 MHz。     

一种高速高增益CMOS运算放大器的设计

设计了一种应用于采样保持电路中高速高增益运算放大器。该运放采用全差分增益提高型共源共栅结构。在输入信号通路上加入适当的补偿电容,消除了零极点对对运放建立时间的影响,同时对主运放的次极点进行了优化,改进了相位裕度。采用0.35μmCMOS工艺仿真,结果表明,运放的开环直流增益达到106dB,单位带宽为831MHz（负载电容8pF）,相位裕度为60.5°,压摆率为586V/μs,满足12位50MS/s流水线ADC中采样保持电路性能要求。     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

0.18μm数字CMOS工艺下的高增益运算放大器设计

基于SMIC 0.18μm数字CMOS工艺,设计了一种基于增益增强技术的折叠式共源共栅运算放大器,并采用衬底校准技术增大了运放的输入摆幅,可用于13位30MHz采样频率的流水线模数转换器,分析了受流水线性能限制的运放性能.仿真结果表明运放在1V的输入摆幅下开环增益大于100dB,8.5pF负载电容下单位增益带宽为322MHz,功耗仅为1.9mW.     

0.18μm数字CMOS工艺下的高增益运算放大器设计

基于SMIC 0.18μm数字CMOS工艺,设计了一种基于增益增强技术的折叠式共源共栅运算放大器,并采用衬底校准技术增大了运放的输入摆幅,可用于13位30MHz采样频率的流水线模数转换器,分析了受流水线性能限制的运放性能.仿真结果表明运放在1V的输入摆幅下开环增益大于100dB,8.5pF负载电容下单位增益带宽为322MHz,功耗仅为1.9mW.     

运算放大器教学中的若干问题探析

针对电路理论课程中运算放大器（运放）的教学，对教学内容中的若干问题进行了讨论。辨析了不同运放模型符号之间的区别，厘清了虚短和虚断概念并给出了正确表述，说明了含运放电路含“地”的必要性，探讨了对含运放电路分析结果所必须进行得校核，指出了现有运放模型在反映放大倍数频率响应方面的局限性。讨论内容对电路理论课中运放相关教学内容的完善有积极意义。     

有源微分电路设计

用理想运放模型设计的有源微分电路的不足表现为，幅频特性有远离微分规律的尖峰，符合微分规律的频带不宽。为此提出在有源微分电路的传递函数中计及实际运放幅频特性，增加与输入电容串联的电阻，可使有源微分电路的幅频特性没有不符合微分规律的尖峰，符合微分规律的频带达到最宽。     

Active biasing of multistage CMOS op-amps for performance enhancement

The technique of active biasing is introduced and applied to a high-gain fully differential two-stage CMOS cascode op-amp, in order to enhance its various performance metrics such as gain, unity gain frequency, common mode and power supply rejection ratios, slew rate and settling time. The improved performance is predicted theoretically and substantiated through circuit simulations.     

Adequate SC model of op-amp with finite DC gain and bandwidth suitable for two-op-amp SC biquad analysis

An adequate model of a nonideal op-amp operating in a two-op-amp SC biquad is derived. The model leads to an equivalent SC circuit containing ideal components. Substitution of any op-amp in an SC biquad by its equivalent SC circuit allows the exact frequency response of the biquad to be found easily, taking into account the finite DC gain and bandwidth of op-amps.     

Wien bridge oscillators using current conveyors

Realization of oscillators with single resistor control based on the circuit techniques of the second generation current conveyors (CC II) utilizing the separability of the Wien RC one-ports that are generalized through appropriate insertion of two more resistors is considered. The relative frequency stability is shown to improve over the conventional op-amp Wien bridge versions.     

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-μm CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of ±2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies     

光栅传感器信号细分中绝对值电路的设计

针对光栅传感器信号精细分中绝对值电路存在的常见问题,以提高测量精度为目标,通过不断改进模拟电路的结构,选取不同型号的运放芯片,同时使电路中的电阻、电容等元器件的参数达到最佳匹配,在不同频率的输入信号作用下,反复调试,最后得出了一种在高频输入的条件下输出信号能高度保真的绝对值电路,从而使光栅传感器对位移测量的分辨力可达到0.01μm。     

Analysis of op-amp phase margin impact on SC ΣΔ modulator performance

The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (ΣΔΜ) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35 μm CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in ΣΔΜ behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase.     

石油测井仪器电流检测系统分析

在测井仪器的研发期间,对仪器的功耗要进行监测,利于可以科学的给仪器搭配适合的电池,为此设计了可以在大动态情况下,连续的对直流的小电流进行监测的检测系统,对于系统有连续监测小电流的独特需求,设计出了运用高输入阻抗的方法和差分运放的I/V转换方法选用放大信号、多级硬件的电路滤波和数字的滤波相综合形式的制止干扰的方法,主要是制止系统内的噪声和系统外在的工频干扰;在此之外还运用软件来达到自动量程的效替来实现大范围的电流检测要求,通过实验来实现使用的需求.     

Failure of Barkhausen oscillation building up criterion: Further evidence

It has been suggested in many textbooks that, given a closed-loop system, oscillation will commence and build up therein if the magnitude of loop gain is greater than unity at the frequency at which the angle of loop gain is zero degree. A novel ideal op-amp based counterexample to this suggestion is presented. The Letter serves to substantiate the findings in a recent Letter. A discussion relating to the finite gain of op-amp is included.