模拟电路设计中匹配器件组版图自动生成技术

目前,大多数模拟版图设计者采用人工方式分析电路图、查找匹配器件组,从而进行手工布局.在大规模集成电路设计中,为了缩短集成电路的设计周期,降低成本,利用C++语言算法开发一款模拟集成电路版图布局自动化的工具.针对模拟电路中匹配器件组的匹配模式不同,根据每种匹配模式的特点编写了相应匹配器件组自动布局的算法,缩短版图的布局时间,从而缩短了设计周期,降低设计成本.通过对每种匹配模式的模拟测试及结果分析,验证了该算法的可行性和有效性.     

浅谈CMOS模拟集成电路版图设计的器件匹配方法

基于模拟集成电路版图设计中的器件不匹配问题,对版图设计中的器件匹配的方法、技巧以及需要注意的问题进行总结,并结合一个运放的版图设计实例详细阐述了版图设计的基本器件匹配方法与技巧。     

低失配CMOS差分放大器的后端版图设计研究

器件尺寸的缩小提高了晶体管的原始速度,但是集成电路不同模块间有害的相互干扰和版图的非理想性都限制了系统的工作速度和精度。理想的差分放大器电路参数是完全对称的,但实际电路中,由于制造工艺每道工序的不确定性,标称相同的器件都存在有限的不匹配。本文在设计差分电路的版图时通过讨论制造工艺和版图结构对电路性能的影响,设计了失配较小,寄生效应小的单管版图结构,并在全局布局时充分考虑了对称性对电路性能的影响得到了比较理想的差分放大器版图。     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个 OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能     

开关电源监控电路版图优化设计

通过完成电路中的各功能模拟和焊盘的合理旋转，对开关电源监控电路和的版图进行了优化设计，在放置器件对考虑可能出向的拴锁，匹配和寄生，使其之间的连线最短，交叉最少，并对芯片面积进行了估算。     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性．提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及STACK内连线的不匹配的模型．基于该模型,一种新的STACK生成方法用来控制版图的寄生参数和匹配特性,优化STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图．一个OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能．     

模拟集成电路模块版图的生成系统

介绍了模拟集成电路模块版图的开发系统.系统用高效的过程化版图描述语言构造模拟模块,编译产生与工艺及应用无关的模块版图生成器.系统的网络识别和模块内布线功能自动完成模块网络的完全连通,基于优选的电气特性驱动版图生成,提高设计可靠性.该系统已辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图.     

层次版图连接关系提取

本文提出了一种新的层次版图连接关系提取算法,其利用投影法和版图倒序树(Inverse Layout Tree,简记为ILT)构建同一原始图形在不同层次单元之间的关联,并在基于边的扫描线算法的基础上利用组合器的方法建立版图数据的正确连接.此算法能够极好的保持版图中原有的层次,在此算法基础上进行的层次网表提取能够使层次LVS得到最大程度的支持;同时,算法具有很高的效率,只需占用很少的资源.目前,九天EDA系列工具中的层次版图验证工具已经采用此算法.     

双极模拟集成电路版图识别的模式识别算法

双极模拟ＩＣ在广泛应用于个人移动通信ＲＦＩＣ中占有重要地位。双极模拟ＩＣ版图识别与验证是其ＣＡＤ研究的重要内容之一。基于模式识别和专家系统的思想,提出了一种双极模拟ＩＣ版图识别的模式识别算法。该方法定义了五种基本版图图形关系,在此基础上构造了版画图技术向量,建立了算法系统及识别系统。该识别算法的优点在于与具体工艺过程无关,从而使识别过程完全系统化。实验表明,该识别系统有效、准确、可靠。     

改进型对称分束偏光棱镜

为了得到对称分束的偏光棱镜,采用了对常规渥拉斯顿棱镜进行改进的方法,即通过修正o光束的出射端面来实现对称分束.得到了o光束出射端面的修正角与棱镜的结构角之间的关系式.以632.8nm波长为例分析了o光束出射端面的修正角与棱镜的结构角之间的关系曲线和修正角与波长的关系曲线.结果表明,此种设计既可实现对称输出,并且具有设计简单,加工方便等特点.     

A technology-independent approach to custom analog cell generation

STAT (schematic to artwork transistor), a set of software tools designed to generate full-custom layouts of analog cells from arbitrary schematic topologies in any IC technology, is described. The system enables the circuit designer to annotate the schematic with component matching and symmetry relationships. Software subroutines are then used to generate device artwork. The placement program implements algorithms in which groups of related components are placed first so that annotated layout constraints are preserved. A novel placement method is offered which recognizes that analog schematic topologies often reflect desirable layout configurations. A flexible multilayer cell-level router has been developed to complete the device interconnection. The STAT system functions in either a polygon or symbolic layout environment. The symbolic layout allows design-rule and technology changes to be made easily and is designed to interface with a commercial compaction program to produce the final layout     

基于关联性的目标动向热点分析

为了从海量传感器数据中及时发现重要目标的动向,提出了一种目标动向信息表征及关联方法,即从多源异类传感器获取的信息中抽取出目标关联要素进行动向表征,利用语义决策树实现动向要素聚类,通过知识规则进行关联匹配扩展,从而发现目标动向的热点,并进一步统计分析目标活动规律与发展趋势。实验表明所提出的基于关联性的目标动向热点分析算法准确率高,具有实用价值。     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

Statistical modeling of device mismatch for analog MOS integratedcircuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms     

Layout-driven memory synthesis for embedded systems-on-chip

Memory-processor integration offers new opportunities for reducing, the energy of a system. In the case of embedded systems, where memory access patterns can typically be profiled at design time, one solution consists of mapping the most frequently accessed addresses onto the on-chip SRAM to guarantee power and performance efficiency. In this work, we propose an algorithm for the automatic partitioning of on-chip SRAMs into multiple banks. Starting from the dynamic execution profile of an embedded application running on a given processor core, we synthesize a multi-banked SRAM architecture optimally fitted to the execution profile. The algorithm computes an optimal solution to the problem under realistic assumptions on the power cost metrics, and with constraints on the number of memory banks. The partitioning algorithm is integrated with the physical design phase into a complete flow that allows the back annotation of layout information to drive the partitioning process. Results, collected on a set of embedded applications for the ARM processor, have shown average energy savings around 34%     

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。     

模拟电路故障诊断的信息融合新方法

针对测试信息不足造成模拟电路故障诊断准确率较低的问题,为充分利用有限测试信息,提出一种模拟电路故障诊断信息融合新方法.首先,将采集的故障样本集变换到不同特征空间,然后利用所提出的马氏距离分布熵求取各特征空间的相对优势分类集,在此基础上,定义相对优势属性约简提取各特征空间的局部最佳可分性信息,最后,对基分类器结合所提出的自适应类模糊密度赋值方法进行模糊积分融合.国际标准电路故障诊断实例表明,所提方法能有效提高模拟电路的故障诊断率.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

基于距离场细化的骨架提取算法

骨架保存了要处理对象的拓扑信息,是图像分析的重要研究内容之一.传统的骨架细化算法不能保证结果的准确性,而距离场的方法无法保证结果的连续性.为此提出一种快速有效的骨架提取算法,将经典的距离变换法和细化方法结合,克服二者之间存在的缺陷,实现算法的互补.经过大量实验验证,此方法能够得到连续、准确的骨架,可以很好地满足实际应用的需求.