一种10位50MHz流水线模数转换器的设计

采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。     

低功耗10位30MS/s流水线A/D转换器

基于0.18μm CMOS混合信号工艺,设计了一个低功耗10位30 MS/s流水线A/D转换器.通过优化各级采样电容和运放(0TA)偏置电流,以及使用动态比较器,大大降低了整体功耗.采用增益自举开关,以减少开关非线性;引入数字校正技术,以提高转换精度.当采样时钟频率为32 MHz、输入信号频率为16 MHz时,信噪失真比(SNDR)为59 Db,无杂散动态范围(SFDR)为71 Db.AD(:核心电路版图面积为0.64 mm2,功耗仅为32 Mw.     

一种新型栅压自举采样开关

基于SMIC 0.18 μm CMOS工艺,设计了一种新型的栅压自举采样开关。采用镜像结构,增加了自举电容。采用时钟控制反相器,减少了MOS采样开关管的栅极节点寄生电容。这些措施有效抑制了电荷共享效应,提高了线性度,提高了采样开关的导通、关断速度。仿真结果表明,在6.25 MHz频率、0.8 V输入正弦波信号、100 MHz采样频率的条件下,该栅压自举采样开关的SFDR为111.3 dBc,SNDR为108.9 dB。     

一种10位80 MS/s低功耗采样保持电路的设计

给出了一种基于开关电容(SC)电路的10位80 MHz采样频率低功耗采样保持电路。它是为一个10位80 MS/s流水线结构A/D转换器的前端采样模块设计的。在TSMC 0.25μmCMOS工艺,2.5 V电源电压下,该电路的采样频率为80 MHz;在奈奎斯特频率采样时,无杂散动态范围(SFDR)为75.4 dB,SNDR为71.8 dB,ENOB为11.6,输入信号范围可达160 MHz(两倍采样频率),此时SFDR仍大于70 dB。该电路功耗为16.8 mW。     

适用于中频采样的CMOS自举采样开关

分析了影响CMOS采样开关性能的非理想因素,针对中频采样A/D转换器对采样开关特性的要求,改进得到了一种新型的CMOS自举采样开关.较之传统栅压自举开关,此新型MOS采样开关能够消除由于阈值电压随输入信号变化所产生的非线性.基于0.18 μm标准CMOS数模混合工艺对电路进行了模拟,模拟结果显示,在输入信号为2.39 MHz正弦波,峰峰值为2V,采样时钟频率为100 MHz时,开关的无杂散动态范围达到116.7 dB,较之传统自举采样开关提高了15dB左右.试验结果表明该栅增压电路非常适用于高速中频采样.     

一种具有改进积分器结构的高阶∑-△调制器

设计了一个五阶单回路∑-△调制器，最高输入信号频率22kHz。通过改进积分器的结构，显著减小了开关电荷注入效应引起的调制器的谐波失真。整个电路采用0．6μm CMOS工艺设计。仿真显示，当采样频率为6MHz时，调制器的SNDR达到123dB，SNR超过125dB，满足18位A／D转换器的精度要求。     

一种高性能CMOS采样/保持电路

提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

适于低电源电压应用的新型MOS自举采样开关

提出了一种适合低电源电压应用的新型MOS自举采样开关电路.通过“复制”自举电容和采样开关作为电荷损耗检测电路,并将检测出的电压降低值重新加到自举电容上,解决了传统MOS自举采样开关在低电源电压下工作时的电荷分享问题.基于0.18μm标准CMOS工艺,对电路进行了仿真.结果显示,在输入频率为60 MHz、峰-峰值为1V、采样频率为125 MHz时,与传统自举采样电路相比,新型自举采样电路采样开关管具有更低的导通电阻,无杂散动态范围( SFDR)提高了8dB,特别适合在低压高速A/D转换器中使用.     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.     

一种新的多值A/D转换器

通过对三值 A/ D转换数学表示的分析 ,设计了二种三值 A/ D转换器电路。该转换器电路具有结构简单、低功耗、小型化和高信息密度等优点 ,它可进一步完善多值数字系统的研究     

单缸汽油发动机电控系统设计

针对传统发动机使用的化油器反应滞后、控制不精确、排放污染大的问题,以某款单缸化油器式汽油发动机为研究对象,设计了基于MC9S12XS128单片机的电子控制系统。文中分析了单片机对A/D转化信号的采集要求,设计了各个传感器的信号处理电路及驱动电路。通过对发动机工作过程的分析,对整个控制程序进行了模块化设计,并对主要模块的控制算法进行了阐述。实验结果表明,该系统使得发动机的动力性得到了提高,最大功率约提高了6.62%,同时提高了经济性,燃油消耗量（每小时油耗）降低了5.26%,验证了电控系统的有效性。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.