半导体器件

0622900电流拥抒效应对GaN基发光二极管可靠性的影响[刊,中]/艾伟伟//激光与红外．—2006,36(6)．—491- 494,503(G) 0622901 PLD在三态采样一保持开关功放中的应用研究[刊,中]/张丹红//电子科技．—2006,(6)．—59-61(D)分析了两态采样一保持策略开关功率放大器的优缺点,提出了一种利用可编程逻辑器件(简称PLD)进行磁力轴承三态采样一保持开关功率放大器设计的方法,并在可编程逻辑器件内部逻辑功能设计的基础上,给出了内部功能的时序仿真图。和传统设计方法相比,该设计具有可以明显减少所使用器件数目,简化线路,减小功率放大器体积,降低设计成本,提高设计效率以及提高功放系统的整体可靠性等优点。参5     

多路数据采集系统中FIFO的设计

首先介绍了多路数据采集系统的总体设计、 FIFO芯片IDT7202.然后分别分析了FIFO与CPLD、AD接口的设计方法.由16位模数转换芯片AD976完成模拟量至位数字量的转换,由ATERA公司的可编程逻辑器件EPM7256A完成对数据的缓存和传输的各种时序控制以及开关量采样时序、路数判别.采用FIFO器件作为高速A/D与DSP处理器间的数据缓冲,有效地提高了处理器的工作效率.     

总线与总线结构

0211676基于CPLD的VXI总线接口的研制〔刊〕/王远//国外电子元器件.-2002,(1).-13～15(C) 文章以VXI总线开关矩阵模块为例,介绍了基于可编程逻辑器件的VXIbus寄存器基接口的开发过程。给出了选用ALTERA公司的可编程逻辑器件     

基于FPGA的数字功率放大器的设计

以可编程器件XC2S200E为核心器件设计了一个数字功率放大器。设计中通过FPGA实现对音频信号的采样控制，并将采样的数字信号转换为脉宽调制（PWM）信号，然后驱动H桥电路，实现功率放大。设计采用先进的FPGA芯片和可靠的同步设计，具有很好的灵活性和稳定性。     

基于可编程逻辑器件的数字电路设计

可编程逻辑器件的出现,使得传统的数字系统设计方法发生了根本的改变,所以有必要介绍一下基于可编程逻辑器件的数字电路设计方法.以计数器的实现方法作为实例,介绍了采用原理图和硬件描述语言两种方法作为输入,实现计数器的方法,并描述了编译仿真的方法,给出了对应的仿真结果.采用熟悉的器件为例,使基于可编程逻辑器件的数字电路设计方法更容易理解掌握.     

用MACH231实现高速32—32位多路转换横杆开关

本文采用三种复杂可编程逻辑器件(CPLD)实现了32-32位多路转换横杆开关,综合比较了其各种指标和性能,并提出了采用MACH器件的最佳方案.     

随机等效采样系统设计及其关键技术点分析

本文采用随机等效采样方法,实现实时40MHz等效4GHz的采样速率.系统在可编程逻辑器件CPLD的时序控制下有序工作,DSP完成数据处理,处理结果通过USB总线送往主机.前端信号调理电路的设计、双斜率时间展宽电路的设计、等效排序算法的设计是设计的关键点所在.     

半导体与微电子技术 半导体器件

0625944自动断电的CPLD〔刊,中〕/Rafael Camarota//电子设计技术.—2006,(7).—104-106(C)0625945复杂可编程逻辑器件的设计技术〔刊,中〕/李文昌//微处理机.—2006,27(3).—14-16(G)介绍了复杂可编程逻辑器件(CPLD)的设计技术,重点叙述了复杂可编程逻辑器件架构的设计,关键单元设计技术。采用0.35μm内嵌Flash工艺进行模拟仿真和全定制版图设计,该复杂可编程逻辑器件(CPLD)具有72个宏单元,系统频率可达85MHz,管脚延时可达7ns。参80625946倒装结构大功率蓝光LEDs的研制〔刊,中〕/伊晓燕//光电子·激光.—2006,17(6).—693-696(E)…     

QuickLogic的PASIC效果和通路链接

现代逻辑电路设计者通过利用由各种各样的半导体构成的开关器件,使逻辑单元互相连接,可以实现出所设计的逻辑电路。器件的基本性能是由所采用的可编程器件的电性能所决定的。换句话说,当逻辑电路的输出/输入信号穿过可编程器件时,由于可编程器件的固有时间常数CR,在逻辑单元里和逻辑单元之间,都要使该信号产生传输延迟时间。这就意味着可     

构成单片正弦波振荡器的可编程模拟电路

可编程逻辑器件为数字设计中复杂功能的实现提供了一种流行的方法。虽然制造商尚未提供能与VLSI数字电路复杂性相比拟的模拟电路,但现场可编程模拟电路正在信号调整和滤波应用中获得广泛采用。这些器件基于CMOS跨导及开关式电容放大器,可为相对复杂的设计问题提供一种便利的解决方案。Lattice     

Class E RF tuned power amplifiers in CMOS technologies: theory and circuit design considerations

The article introduces several configurations of class E power amplifiers in CMOS technologies. Each configuration, however, alleviates some problems in the design of class E power amplifiers. The two-stage class E power amplifier reveals the design technique for the driving stage, which provides a more efficient driving signal in terms of class E operation. The complementary configuration takes advantage of the symmetrical circuit topology, which allows much lower total harmonic distortion in the output signal. The power-adaptive technique based on high-Q varactors gives a more feasible and effective approach to achieving the function of output power control for switching-mode power amplifiers. An approach to implement linear power amplification using switching mode power amplifiers is also introduced that can achieve linear amplification while still keeping high power efficiency and output power.     

可编程逻辑器件设计新思路

可编程逻辑器件在集成电路的发展中占有重要地位。深亚微米与超深亚微米技术的发展使可编程逻辑器件向系统级可编程芯片转移。本文详细阐述了基于IP的系统级可编程芯片的设计策略。     

High Precision Motion Control of Servo Drives

In this paper, we investigate the advantages and feasibility of motor control using very fast (in megahertz) switching in place of traditional amplifiers. We also propose integrated motion-control architecture based on discrete-event control approach to be implemented in digital logic at an equally high rate. A switching controller combines the current and motion feedback paths into a single loop. A model-based observer estimates the load torque. When compared to second-order controllers implemented with traditional amplifiers, the proposed design promises increased performance, better efficiency, and improved load estimation. Simple implementation makes concepts of switching control very attractive in motion-control systems like control of dc or ac servomotors. The control algorithm designed by the proposed approach can be easily implemented on field programmable gate array platforms.     

前、后向多抽运光纤喇曼放大器的增益特性分析

为了研究前向、后向多抽运光纤喇曼放大器的增益特性,在受激喇曼散射功率耦合方程组的基础上,采用龙格-库塔法结合打靶法分别计算了前、后向抽运功率、信号功率沿光纤的演化过程,并给出了抽运功率和信号功率的计算结果.结果表明,前向抽运系统中信号开始被放大,在最大处开始快速减小.低频抽运光的功率开始被放大的原因是由于抽运光之间的非线性相互作用引起的.后向抽运时信号开始被缓慢减小,然后在距离光纤末端处快速增加.这为以后喇曼光纤放大器的设计提供了重要的参考.     

前、后向多抽运光纤喇曼放大器的增益特性分析

为了研究前向、后向多抽运光纤喇曼放大器的增益特性,在受激喇曼散射功率耦合方程组的基础上,采用龙格-库塔法结合打靶法分别计算了前、后向抽运功率、信号功率沿光纤的演化过程,并给出了抽运功率和信号功率的计算结果。结果表明,前向抽运系统中信号开始被放大,在最大处开始快速减小。低频抽运光的功率开始被放大的原因是由于抽运光之间的非线性相互作用引起的。后向抽运时信号开始被缓慢减小,然后在距离光纤末端处快速增加。这为以后喇曼光纤放大器的设计提供了重要的参考。     

Robust current controller for three-phase inverter usingfinite-state automaton

A novel feedback current controller for a three-phase load driven by a power inverter is proposed. The main design specifications are robustness to load electrical parameters, fast dynamical response, reduced switching frequency, and simple hardware implementation. To meet previous specifications a multi-variable hysteresis type controller is proposed, designed as a finite-state automaton and implemented with a programmable logic device. After a general introduction, system analysis is performed, control targets are specified, and the proposed control strategy is presented and discussed. Further, actual controller architecture, based on simple analog-logic hardware, is shown and experimental results are presented using an induction motor as the inverter load. However, this does not limit the wider applicability of the proposed controller that is suitable for different types of three-phase AC loads     

Ultra-high speed modulation-doped field-effect transistors: atutorial review

A tutorial review on the modulation-doped field-effect transistor (MODFET) and its application to ultra-low-noise, medium-power, and ultra-wide-band traveling-wave amplifiers as well as ultra-high-speed digital logic circuits is presented. It is believed that with further advances in material growth and device scaling significant improvements in cutoff frequencies, switching speed, noise, and power will be achieved in the near future     

Integrated circuit design for physical unclonable function using differential amplifiers

A physical unclonable function (PUF) based on process variations on silicon wafers is a very promising technology which finds various applications in identification and authentication, but only a few integrated circuits have been reported so far. As those circuits are vulnerable to power supply noises, switching noises and environmental variations, they lead to a reliability issue such as time-varying or metastable responses. To resolve this issue, this letter proposes a new integrated circuit design for PUFs using differential amplifiers. The feasibility of the proposed circuit has been theoretically analyzed and validated through HSPICE simulations for the previous and proposed circuits.     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.