Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

粘结层空洞对功率器件封装热阻的影响

功率器件的热阻是预测器件结温和可靠性的重要热参数,其中芯片粘接工艺过程引起的粘结层空洞对于器件热性能有很大的影响。采用有限元软件Ansys Workbench对TO3P封装形式的功率器件进行建模与热仿真,精确构建了不同类型空洞的粘结层模型,包括不同空洞率的单个大空洞和离散分布小空洞、不同深度分布的浅层空洞和沿着对角线分布的大空洞。结果表明,单个大空洞对器件结温和热阻升高的影响远大于相同空洞率的离散小空洞;贯穿粘结层的空洞和分布在芯片与粘结层之间的浅空洞会显著引起热阻上升;分布在粘结层边缘的大空洞比中心和其他位置的大空洞对热阻升高贡献更大。     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100 mm² without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter.     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

A study of large area die bonding materials and their corresponding mechanical and thermal properties

We tested the ability of Au/Sn eutectic, silver paste, and solder paste to bond to a large area as well as the bonding of a high power LED die to a highly conductive submount. The samples ran through several tests including ultrasound image, shear force, and thermal resistance measurement. Finite element analysis (FEA) models were built for comparison and analysis. Au/Sn bonding shows the best thermal and mechanical properties. Silver paste shows lower contact thermal resistance compared with solder paste. Although the thickness of the silver paste bonding layer is greater than the solder paste bonding layer, the average total thermal resistance is noticeably lower than the solder paste bonded samples.     

Heat dissipation assessment of through silicon via (TSV)-based 3D IC packaging for CMOS image sensing

The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging) designed for CMOS image sensing under natural convection through finite element analysis (FEA) and thermal experiments. To enhance modeling and computational efficiency, an effective approach based on FEA incorporating a 3D unit-cell model is proposed for macroscopically and thermally simulating the heterogeneous TSV chips. The developed effective thermal conductivities are compared against those obtained from a rule-of-mixture technique. In addition, the proposed numerical models are validated by comparison with two experiments. Besides, the uncertainties in the input chip power from the specific power supply and in the measured chip junction temperature by the thermal test die are evaluated. Finally, a design guideline for improved thermal performance is provided through parametric thermal study.     

Reliability of Lead-Free Solder Interconnections in Thermal and Power Cycling Tests

Lead-free solder interconnection reliability of thin fine-pitch ball grid array (BGA) lead-free packages has been studied experimentally as well as with finite-element (FE) simulations. The reliability tests were composed of the thermal shock test, the local thermal cycling test (resistors embedded in the board around the package), and the power cycling test (heat generation in the die). A 3-D board-level finite-element analysis (FEA) with local models was carried out to estimate the reliability of the solder interconnections under various test conditions. Due to the transient nature of the local thermal cycling test and the power cycling test, a sequential thermal-structural coupling analysis was employed to simulate the transient temperature distribution as well as the mechanical responses. Darveaux's approach was used to predict the life time of the solder interconnections. Furthermore, the numerical results validated by the experimental results indicated that the diagonal solder interconnections beneath the die edge were the most critical ones of all the tests studied here. It has been found that the fatigue life in the power cycling test was much longer than that in the other two tests. Detailed discussions about the failure mechanism of solder interconnections as well as the microstructural observations of the primary cracks are reported in this paper.      

Effect of type of thermo-mechanical excursion on growth of interfacial intermetallic compounds in Cu/Sn-Ag-Cu solder joints

This study reports the effect of different types of thermo-mechanical excursion (TME) on growth of intermetallic compound (IMC) layer formed at the interface of Sn-3.0%Ag-0.5%Cu solder and Cu substrate. 1 mm thick solder joints were prepared by reflowing at 270 °C for either 60 or 90 s. Solder joints were then exposed to one of the following TME: (i) isothermal aging at 60 °C for 48, 96 and 144 h, (ii) thermal cycling between − 25 and 125 °C for 100, 200 and 400 cycles, and (iii) thermo-mechanical cycling between − 25 and 125 °C for 100, 200 and 400 cycles, wherein a shear strain of 10% per cycle was imposed on the joint. Finite element analysis (FEA) was performed to ascertain the effects of imposed shear strain and volumetric expansion due to the formation of IMC on the stress field in the solder joint. Irrespective of the type of TME, the thickness of the IMC layer increased with time. However, IMC thickness increased relatively more rapidly under thermo-mechanical cycling condition, indicating strain enhanced coarsening of the interfacial IMC layer. FEA showed that high stresses were generated in the IMC layer and near solder-IMC interface due to the formation of IMC layer as well as imposed external strain, which might then not only enhance the IMC growth kinetics, but also affect the morphology of the IMC layer.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Application of the Taguchi method to chip scale package (CSP)design

A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYS^TM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L₁₈ Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls     

Improved thermal fatigue reliability for flip chip assemblies usingredistribution techniques

The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

Characterization of the Effect of Shape Memory Alloy on Solder Joint Strength Through Modeling and Testing

Currently some of the most common problems that surface mount technology encounters are warpage, delamination, and inelastic strain concentration accumulated in the solder joint during thermal cycling because of mismatch of thermal expansion coefficient between the package and chip side. Material as well as package structure are the critical issues with respect to these problems. The objective of this research is to investigate how shape memory alloy (SMA) applied in the under bump metallization (UBM) can affect solder joint reliability under thermal mechanical stress. Joint strength tests revealed the better strength of solder joints with SMA UBM after accelerated thermal cycling test. Finite element modeling as well as multilayer stress calculations revealed less strain accumulated in the solder and more stress concentrated in Si in the solder joint with SMA UBM. A mechanism by which the SMA accommodates most of the stress and strain caused by the mismatch of the thermal expansion coefficients was proposed to explain the reinforcement of the solder joint by the SMA UBM.     

基于稳健设计的PBGA器件焊点热机械疲劳可靠性的优化设计

基于稳健设计与有限元法,研究了加速热循环测试条件下塑封球栅阵列(PBGA)焊点的热机械疲劳可靠性.考虑PCB大小(A)、基板厚度(D)、硅片热膨胀系数(G)、焊点热膨胀系数(H)等八个控制因素,使用L₁₈(2¹×3⁷)混合正交表,以对焊点热机械疲劳寿命的考核为目标,对PBGA焊点进行了优化设计.结果表明,影响焊点可靠性的显著性因素依次是基板热膨胀系数、焊点的热膨胀系数、基板厚度、芯片的热膨胀系数;最优方案组合为A1B2C3D1E2F1G3H1.进一步的验证试验结果表明,与原始方案相比,该优化方案的最大等效应变降低了66%,信噪比提高了22.4％.     

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.