Fully synthesised decimation filter for delta-sigma A/D converters

Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a fully synthesised digital decimation filter that provides a time-to-market advantage. The filter consists of a cascaded integrator-comb filter and two cascaded half-band FIR filters. A canonical signed-digit representation of the filter coefficients is used to minimise the area and to reduce the hardware complexity of the multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated by using 0.25-μm CMOS technology with an active area of 1.36 mm² and shows 4.4 mW power consumption at a clock rate of 2.8224 MHz. Experimental results show that this digital decimation filter is suitable for use in oversampled data converters and can be applied to new processes requiring a fast redesign time. This is possible because the filter does not have process-dependent ROM or RAM circuits.     

应用于ΣΔADC的抽取滤波器的设计与实现

介绍了一种应用于ΣΔADC的抽取滤波器的设计和电路实现方法.通过对传统设计方法的分析,提出了一种可以节省10%硬件利用率的改进方法,同时提出了一种适用于半带滤波器的串并联结构,与传统的半带滤波器相比能够提高50%的硬件利用效率.在面积、速度和功耗的折衷的情况下,灵活应用CSD、CSE和多相分解结构,在0.18μm下实现了0.59 mm2的16位数字抽取滤波器.该滤波器与不应用串并联结构的滤波器相比能够节省18%左右的芯片面积.     

Low-power design of decimation filters for a digital IF receiver

This paper presents low-power design techniques at the architectural level for design of decimation filters in a digital IF receiver for wide-area wireless data networks. A multimode decimation filter design implementing both Mobitex and Ardis networks is described. The power is reduced by a factor of 1422 and the area reduced by a factor of 7.85 compared to an optimized single-mode two-stage design. A new multistage decimation filter design tool is also presented, which compares alternative architectures on figures of merit which the low-power designer can map into technology-dependent area and power costs     

基于IP核的滤波器复用模块的设计和实现

介绍了一种基于FIRIP核的抽取滤波器复用模块的设计和实现。FIRIP核可以进行灵活的参数设计,实现不同应用的滤波器设计。以FIRIP核为对象进行FIR滤波器算法的参数选择设计,并以128路的抽取滤波算法为例,在充分考虑到了滤波器特性、FPGA资源分配的诸多因素基础上,利用FIRIP核构建了合理的抽取滤波和复用模块,完成了128路信号的抽取滤波设计和实现。     

12位Sigma-Delta模数转换器的降采样滤波器设计

一种由SNR（信噪比）驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位Sigma-Delta模数转换器的要求。     

多相抽取滤波器的FPGA实现

信号的多相分解在多抽样率信号处理中有着重要的作用.介绍了多相分解的基本理论,结合FIR抽取滤波器的多相分解形式,用Verilog HDL语言来实现2倍抽取滤波器的多相结构,QuartusⅡ软件仿真输出波形,并且用MATLAB对仿真结果进行验证并作比较.结果正确,最后将编程数据文件下载到FPGA芯片上.多相抽取滤波器的设计方法是可行的,整个设计过程由软件实现,参数易于修改.     

A switched-capacitor preprocessor for speech recognition

A switched-capacitor (SC) preprocessing system (preprocessor) which extracts and emphasizes the local peaks of the spectrum in real time is proposed for speech recognition systems. Main components of the system are a specially designed bandpass filter bank, a low-pass decimation filter bank, two-dimensional local peak extraction (LPE) filters, and a LPE filter selection circuit. Furthermore, a SC cascaded integrator-comb filter design technique is proposed to realize the decimation low-pass filter and the LPE filter. Finally, the system is tested by using two speech recognition systems.     

软件无线电数字中频处理的优化设计

软件无线电是目前通信领域研究的热点,其关键技术之一数字中频技术是多速率信号处理理论的典型应用。本文研究了窄带信号条件下,高倍抽取的数字下变频设计,重点分析了基于CIC滤波器和HB滤波器的多级抽取算法。经比较,该设计比单级多相抽取设计节省98.8％的资源,完全可在单片FPGA内实现,而且,滤波性能优于设计指标要求。     

A 16-bit 250-kHz delta-sigma modulator and decimation filter

This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-μm CMOS technology. It achieves a dynamic range of 94 db     

A Low-Complexity Uniform and Non-uniform Digital Filter Bank Based on an Improved Coefficient Decimation Method for Multi-standard Communication Channelizers

It has been shown in literature that the coefficient decimation (CD) techniques can be efficiently used to realize low-complexity finite impulse response (FIR) filters with flexible frequency responses. In this paper, we propose a novel filter bank (FB) design technique based on the combination of the conventional coefficient decimation method (CDM) and the modified coefficient decimation method recently proposed by us. In the proposed FB, subbands of desired bandwidths are obtained by the spectral subtraction of the lowpass and highpass frequency responses obtained after performing CD operations on the prototype filter, using appropriate decimation factors. The proposed FB that provides uniform as well as non-uniform subbands can be used for multi-standard channelization in wireless communication receivers. We show that the proposed FB has a significantly lower complexity along with superior stopband and transition band characteristics when compared with the conventional CDM-based progressive decimation filter bank (PDFB). The design example shows that the proposed FB offers 74 % reduction in multiplication complexity over the PDFB, when used for non-uniform multi-standard channelization with a fixed frequency channel distribution. If the same FB is used for multi-standard channelization with variable locations of the frequency channels, a substantial 95.67 % reduction in multiplication complexity is achieved over the PDFB.     

On the use of interpolated second-order polynomials for efficientfilter design in programmable downconversion

Interpolated second-order polynomials (ISOPs) are proposed to design efficient cascaded integrator-comb (CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOPs can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOPs are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified halfband filter (MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for programmable downconverter is a cascade of a CIC filter, an ISOP, MHBFs, and a programmable finite impulse response filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones     

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a Σ∆ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm² silicon area in 0.13 μm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

一种新的多频连续波雷达数据采集系统设计

给出了一种基于多速率信号处理的多频连续波雷达数据采集系统设计和实现方法。分析了抽取的时域和频域特性,针对多频连续波雷达的应用背景,分析了实际系统中抽取比的选择,设计了合适的抗混叠滤波器。给出了一种FIR实现信号抽取的高效结构。在此基础上,完成了数据采集系统的硬件设计和软件设计。该方案具有控制灵活,数据传输高速、稳定等特点。该设计已经成功应用于实际系统。     

级联COSINE滤波器在抽取滤波中的研究

为了解决高速抽取滤波器系统中传统CIC滤波器旁瓣抑制不够的问题,通过对级联COSINE抽取滤波器和传统CIC抽取滤波器的原理推导进行对比,分析出级联COSINE滤波器在幅频特性上同CIC滤波器具有很大相似之处,且在满足高速抽取滤波器的情况下,同时具备很好的低通特性和硬件实现性。通过MATLAB仿真实验得到,级联COSINE滤波器在进行32倍整数抽取时,第一旁瓣衰减约是传统CIC滤波器的2倍,进而说明相对于传统CIC滤波器,级联COSINE滤波器具有更好的旁瓣抑制性能。     

A high-performance,low-power ∑Δ ADC for digital audio applications

A high-performance low-power ∑Δ analog-to-digital converter (ADC) for digital audio applications is described.It consists of a 2-1 cascaded ∑Δ modulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficientoptimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2,which dissipates only 2.1 mA quiescent current in the analog circuits.     

Trigonometrical approach to design a simple wideband comb compensator

This paper presents a trigonometrical approach to design a simple second order wideband compensator of a comb decimation filter. The method is based on the similarity of the inverse passband comb characteristic and the squared sine function. The design parameter B, which is the amplitude of the squared sine function, depends only on the number K of the cascaded comb filters. Considering that the parameter B can be expressed in terms of only addition and shift operations, we may obtain a multiplierless filter. The proposed filter performs wideband compensation efficiently using a maximum of four additions/subtractions, and for a given K, can be applied to any value of the decimation factor M.     

基于FPGA的数字化正交解调接收机最优设计

结合抽取滤波器的多项滤波结构,在一定条件下,推导出了一种含抽取正交解调接收机最优结构设计方法。在FPGA乘法器资源相同的条件下,采用最优结构设计的接收机内部FIR滤波器阶数比直接实现形式高了近4倍。最后给出了设计实例。     

基于多相结构和部分锐化的CIC抽取滤波器

该文将传统的CIC(Cascaded Integrator Comb)滤波器传递函数分解为递归和非递归部分,可独立调整两者的级联因子;对递归部分进行尖锐化处理改善滤波器的通带衰落,利用电路的等价交换性将抽取因子提前使其工作在低采样率;对非递归部分进行多相分解,实现高速滤波。计算机仿真表明:与传统的CIC、锐化CIC滤波器相比,改进的CIC具有好的通阻带特性;并从通带衰落和混叠抑制的角度,分析了递归和非递归部分的级联因子的取值对整个改进的CIC滤波器特性的影响。     

Integrated switched-capacitor low-pass filter with combined anti-aliasing decimation filter for low frequencies

A new combined antialiasing decimation filter is presented which allows the implementation of a low-frequency switched-capacitor filter on a single chip. Experimental results are presented for a CMOS second-order low-pass filter with 1 dB passband ripple, a cutoff frequency of 2 Hz, and a dynamic range of 84 dB. The decimation filter converts the input clock of 16 kHz into an output clock of 250 Hz. The integrated anti-aliasing filter has a low pole frequency of about 3 kHz.