一种基于0.13m CMOS工艺的10位SAR A/D转换器

基于SMIC0.13μm CMOS1P6M Logic工艺,采用一种新型R-C组合式D/A转换结构、伪差分比较结构以及低功耗电平转换结构设计了一种用于多电源SoC的10位8通道逐次逼近型A/D转换器。在3.3V模拟电源电压和1.2V数字电源电压下,测得DNL和INL分别为0.31LSB和0.63LSB。当采样频率为1MS/s,输入信号频率为490kHz时,测得的SFDR为67.33dB,ENOB为9.48bits,功耗为3.25mW。该A/D转换器版图面积为318μm×270μm,能直接应用于嵌入式多电源SoC。     

一种用于触摸屏SoC的10位200kS/s SAR ADC IP核

采用“5MSBs (Most-Significant-Bits) + 5LSBs (Least-Significant-Bits)”C-R混合式D/A转换方式以及低失调伪差分比较技术,结合电容阵列对称布局以及电阻梯低失配版图设计方法,基于0.18µm 1P5M CMOS Logic工艺,设计实现了一种用于触摸屏SoC (System-on-Chip)的8通道10位200kS/s逐次逼近型A/D转换器IP核。在1.8V电源电压下,测得的微分非线性误差和积分非线性误差分别为0.32LSB和0.81LSB。在采样频率为200kS/s,输入频率为91kHz时,测得的无杂散动态范围(SFDR: Spurious-Free Dynamic Range)和有效位数(ENOB: Effective-Number-of-Bits)分别为63.2dB和9.15bits,功耗仅为136µW。整个A/D转换器IP核的面积约为0.08mm2。设计结果显示该转换器满足触摸屏SoC的应用要求。     

0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种10位200kS/s65nm CMOS SAR ADC IP核

 该文基于65 nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register,SAR) A/D转换器(Analog-to-Digital Converter,ADC) IP核。在D/A转换电路的设计上,采用“7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit)” R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322μm×267 μm。在2.5 V模拟电压以及1.2 V数字电压下,当采样频率为200 kS/s,输入频率为1.03 kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2 dB和9.27,功耗仅为440 μW,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。     

一种14位400MS/S分段型电流舵DAC的设计

基于TSMC O.25μm CMOS工艺,采用分段开关电流结构,设计了一种基于2.5 V电源电压的14位400MS/s D/A转换器.该D/A转换器内置高精度带隙基准源、高速开关驱动电路和改进的Cascode单位电流源电路,以提高性能.D/A转换器的积分非线性(INL)和微分非线性(DNL)均小于0.5 LSB.在400 MHz采样频率、199.8 MHz输出信号频率时,其无杂散动态范围(SFDR)达到85.4 dB.     

一种输出端电压达到负电源电压的DAC缓冲运放

基于2 μm SOI CMOS工艺,设计了一种输出电压达负电源的运放,用作12位四通道D/A转换器的单位增益缓冲。分别在VDD=+5 V,VSS=0 V,VREFH=2.5 V,VREFL=0 V以及VDD=+15 V,VSS=-15 V,VREFH=10 V,VREFL=-10 V这两种条件下测试D/A转换器性能,该转换器的INL分别为-0.31 LSB和0.27 LSB。测试结果表明,该运放的性能满足D/A 转换器的要求。     

14位50MS/s100mW0.18μm CMOS流水线ADC

实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。     

低功耗、全差分流水线操作CMOS A/D转换器

提出一种基于运算跨导放大器共享技术的流水线操作A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗和面积.采用这种结构设计了一个10位20MS/s转换速率的全差分流水线操作A/D转换器,并用CSMC 0.6μm工艺实现.测试结果表明,积分非线性为1.95LSB,微分非线性为1.75LSB;在6MHz/s采样频率下,对1.84MHz信号转换的无杂散动态范围为55.8dB;在5V工作电压、20MHz/s采样频率下,功耗为65mW.     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

9位100 MSPS流水线结构A/D转换器的设计

提出一种采用三级流水线型结构的9位100 MSPS折叠式A/D转换器,具体分析了其内部结构。电路使用0.6 μm Bipolar工艺实现, 由5 V/3.3 V双电源供电, 经优化设计后, 实现了9位精度,100 MSPS的转换速度,功耗为650 mW,差分输入范围2.2 V。给出了在Cadence Spectre的仿真结果,讨论了流水线A/D转换器设计的关键问题。     

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm² in a 1 μm CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip     

The implementation of digital echo cancellation in codecs

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5-μm technology using ΣΔ modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary     

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

Low power consumption and small chip area (2.09 mm×2.15 mm) are achieved by introducing a new architecture to a subranging A/D converter. In this architecture, both coarse and fine A/D conversions can be accomplished. Consequently, a large number of comparators and processing circuits have been removed from the conventional subranging A/D converter. This architecture has been realized by the introduction of a chopper-type comparator with three input terminals which makes both coarse and fine comparisons by itself. The A/D converter has two 8-b sub/A/D converters which employ this new architecture, and they are pipelined to improve the conversion rate. Good experimental results have been obtained. Both the differential and the integral nonlinearity are less than ±0.5 LSB at a 20-megasample/s sample frequency. The effective resolution at 20-megasample/s sampling frequency is 7.4 b at a 1.97-MHz input frequency and 6.7 b at a 9.79-MHz input frequency. The A/D converter has been fabricated in a 1-μm CMOS technology     

A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals

A 10-b pipelined analog-to-digital converter (ADC) is presented which makes extensive use of differential current-mode signals. The converter samples at 20 MHz and has an analog bandwidth exceeding 100 MHz. The architecture incorporates the design of a wide-bandwidth, fully differential current-in, current-out track-and-hold (T/H) amplifier differential flash A/D converters, and fully segmented D/A converters. A unique reference distribution technique allows precise trimming of the gains of the DACs and flash converters. The converter is built on a 2-μm BiCMOS process with thin film resistors     

Digital implementation of mismatch shaping in oversampled pipelineA/D converters

Pipeline A/D converters are usually implemented with switched capacitor technology. The effect of gain errors caused by capacitor mismatch may be attenuated using mismatch-shaping techniques. The author introduces an architecture that improves the SFDR of a particular pipeline A/D converter, simply by adding digital hardware to the existing analogue design     

基于DSP与CPLD的多通道数据采集系统的设计

设计了利用TI公司的TMS320LF2407A系列DSP和Altera公司的MAXII EPM570系列CPLD控制MAXI M公司的MAX194 A/D转换器实现一个多通道数据采集系统的结构。分析了MAX194 A/D转换器的工作性能,使用Altera公司的MAXII EPM570系列CPLD在QuartusⅡ环境下使用VHDL语言实现了MAX194的模数转换器接口。介绍该系统的工作原理,并详细描述了CPLD,DSP以及MAX194之间具体的硬件电路接口的设计以及软件的实现。     

一种视频8位D/A转换器的新设计

基于0.5μm Double Poly Double Metal CMOS工艺,设计了一种基于5V电压的8位32MHz CMOSD/A转换器,权衡面积和性能的关系,提出了6+2分段式的电流舵结构。该D/A转换器内置改进的高速开关驱动电路和改进的单位电流源电路等,以提高性能。通过多次实验分析,并在Cadence软件上实现了软件仿真,全部功能正常实现,符合设计要求。     

A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers

A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm²