光通信系统中基于LDPC码的SFEC码型研究

基于光通信系统中低密度奇偶校验(LDPC)码型的构造原则和构造方法,构造了适用于光通信系统中冗余度为6.69%的新颖LDPC(3969,3720)和冗余度为4.56%的新颖LDPC(8281,7920)码。仿真分析表明:在10-12的误码率(BER)时,这两种新颖码型在迭代18次后的净编码增益(NCG)分别比ITU-TG.975中RS(255,236)码的NCG大1.63dB和1.49dB,并且LDPC码的译码可在硬件上并行实现;这两种新颖码型的译码速度相当快,与ITU-TG.975.1中级联码型相比,这两种LDPC码的实现复杂度要低得多,可在将来的硬件实现中节省存储空间和减少计算量。因而,所构造的这两种新颖LDPC码型都可作为超验前向纠错(SFEC)码的候选码型。     

光通信系统中一种新颖LDPC码构造方法的研究

基于SCG（4,k）码的构造方法提出了一种改进的新颖低密度奇偶校验（LDPC）码构造方法,该方法比改进前的SCG（4,k）码构造方法在硬件实现方面具有节省存储空间和降低计算复杂度的优点。采用该方法构造了冗余度为5.42%的LDPC（5929,5624）码,仿真分析表明,该码型比已广泛用于光通信系统中的经典RS（255,239）码具有更好的纠错性能与较低的译码复杂度。     

LDPC码在BPSK通信系统中的性能分析

LDPC编码在长码条件下具有接近Shannon极限的纠错能力,但是译码较为复杂,因此分析LDPC编码在短码条件下的编译码性能对于扩大LDPC编码的应用范围,降低译码设备的复杂度有着重要的意义。针对较短LDPC编码情况下的判决译码在BPSK系统中的应用,对基于BP算法的几种软判决译码算法进行了介绍,对算法在BPSK系统中的译码性能进行了仿真,仿真结果表明:基于对数测度的BP算法在LDPC短码条件下有着优良的译码性能,能够有效降低通信系统中编译码的复杂度。     

光通信系统级联码的仿真研究

随着光通信技术向更长距离、更大容量和更高速度的进一步发展,有必要深入研究性能更好的FEC码型方案。在光通信应用的众多FEC码型中,级联码具有短码的复杂度和长码的性能,具有极强的纠突发和纠随机错误的能力,是光通信系统中高效编码的主要研究对象。文中主要对RS-BCH型级联码进行了理论分析及建模仿真,与一般循环码相比该级联码纠错性能优良、冗余度适中、易于实现,更适用于高速光通信系统。     

LDPC编译码算法分析

低密度奇偶校验(LDPC)码是一种线性分组码,其纠错能力可以接近香农极限。针对LDPC码的编译码问题,分析了校验矩阵的构造方法。给出了LDPC码的编码算法以及算法的实现结构。分析了基于软判决的置信传播(BP)译码算法,并给出了可以进一步降低计算复杂度的简化译码方法。通过仿真对比了不同的译码算法在高斯信道下的译码性能。     

一种低译码复杂度的Turbo架构LDPC码

针对低密度奇偶校验(LDPC)码较大的译码复杂度和RAM占用,该文提出了一种低译码复杂度的Turbo架构LDPC码并行交织级联Gallager码 (Parallel Interleaved Concatenated Gallager Code,PICGC)。该文给出了PICGC的设计方法和编译码算法,并分析比较了PICGC译码器与LDPC译码器所需的RAM存储量,推导出RAM节省比的上界。理论分析和仿真结果表明,PICGC以纠错性能略微降低为代价,有效地降低译码复杂度和RAM存储量,且译码时延并未增加,是一种有效且易于实现的信道编码方案。     

串行级联LDPC码及其传输性能分析

提出了一种简化的LDPC译码算法,以减小译码算法的复杂度.以非规则LDPC码作为内码,串联一个高码率规则LDPC码作为外码,可降低或消除错误平层.将此串行级联LDPC码在M-QAM调制信道上进行了仿真分析,结果表明其性能优于RS码,可有效利用带宽,同时保证数据可靠传输.     

低复杂度的LDPC码联合编译码构造方法研究

LDPC码因为其具有接近香农限的译码性能和适合高速译码的并行结构,已经成为纠错编码领域的研究热点。LDPC码校验矩阵的构造是基于稀疏的随机图,所以该类码字编码和译码的硬件实现比较复杂。以单位阵的循环移位阵为基本单元,构造LDPC码的校验矩阵,降低了LDPC码在和积算法下的译码复杂度。同时考虑到LDPC码的编码复杂度,给出了一种可以简化编码的结构。针对该方案构造的LDPC码,提出了消除其二分图上的短圈的方法。通过大量的仿真和计算分析,本文比较了这种LDPC码和随机构造的LDPC码在误码率性能,圈长分布以及最小码间距估计上的差异。     

基于MS-offset的多边类型LDPC码译码算法研究

介绍了多边类型LDPC码,对一种易于硬件实现简化的最小和积补偿算法（MS-offset算法）进行研究并应用在多边类型LDPC码中,通过算法仿真完成了其性能对比分析,利用Verilog语言完成该算法的实现。该算法简化了硬件实现的复杂度,降低了资源消耗。     

一种光通信中基于LDPC码的新颖级联码

基于SCG(4,k)码的构造方法对SCG-LDPC码进行优化改进,构造一种适用于光通信系统的新颖LDPC(3969,3720)码,通过增大其码长,构造码率为95.1%的新颖SCG-LDPC(6561,6240)码,使其码率更符合光通信系统的高码率要求。并用SCG-LDPC(6561,6240)码与码率为94.5%的BCH(127,120)码进行级联,构造出一种新颖的BCH(127,120)+LDPC(6561,6240)级联码。仿真分析表明:在误码率为10-7时,新构造的BCH(127,120)+LDPC(6561,6240)级联码的净编码增益比已广泛应用于光通信系统的经典RS(255,239)码和SCG-LDPC(6561,6240)码分别提高了2.27dB和0.49dB。因而该级联码更适合于光通信系统。     

Performance analysis and code optimization of low densityparity-check codes on Rayleigh fading channels

A numerical method has been presented to determine the noise thresholds of low density parity-check (LDPC) codes that employ the message passing decoding algorithm on the additive white Gaussian noise (AWGN) channel. In this paper, we apply the technique to the uncorrelated flat Rayleigh fading channel. Using a nonlinear code optimization technique, we optimize irregular LDPC codes for such a channel. The thresholds of the optimized irregular LDPC codes are very close to the Shannon limit for this channel. For example, at rate one-half, the optimized irregular LDPC code has a threshold only 0.07 dB away from the capacity of the channel. Furthermore, we compare simulated performance of the optimized irregular LDPC codes and turbo codes on a land mobile channel, and the results indicate that at a block size of 3072, irregular LDPC codes can outperform turbo codes over a wide range of mobile speeds     

Iterative decoding for partial response (PR), equalized,magneto-optical (MO) data storage channels

Turbo codes and low-density parity check (LDPC) codes with iterative decoding have received significant research attention because of their remarkable near-capacity performance for additive white Gaussian noise (AWGN) channels. Previously, turbo code and LDPC code variants are being investigated as potential candidates for high-density magnetic recording channels suffering from low signal-to-noise ratios (SNR). We address the application of turbo codes and LDPC codes to magneto-optical (MO) recording channels. Our results focus on a variety of practical MO storage channel aspects, including storage density, partial response targets, the type of precoder used, and mark edge jitter. Instead of focusing just on bit error rates (BER), we also study the block error statistics. Our results for MO storage channels indicate that turbo codes of rate 16/17 can achieve coding gains of 3-5 dB over partial response maximum likelihood (PRML) methods for a 10^-4 target BER. Simulations also show that the performance of LDPC codes for MO channels is comparable to that of turbo codes, while requiring less computational complexity. Both LDPC codes and turbo codes with iterative decoding are seen to be robust to mark edge jitter     

A high‐performance belief propagation decoding algorithm for codes with short cycles

The simplicity of decoding is one of the most important characteristics of the low density parity check (LDPC) codes. Belief propagation (BP) decoding algorithm is a well‐known decoding algorithm for LDPC codes. Most LDPC codes with long lengths have short cycles in their Tanner graphs, which reduce the performance of the BP algorithm. In this paper, we present 2 methods to improve the BP decoding algorithm for LDPC codes. In these methods, the calculation of the variable nodes is controlled by using “multiplicative correction factor” and “additive correction factor.” These factors are obtained for 2 separate channels, namely additive white Gaussian noise (AWGN) and binary symmetric channel (BSC), as 2 functions of code and channel parameters. Moreover, we use the BP‐based method in the calculation of the check nodes, which reduces the required resources. Simulation results show the proposed algorithm has better performance and lower decoding error as compared to BP and similar methods like normalized‐BP and offset‐BP algorithms.     

A new high rate code scheme with highly parallel and low complexity decoding algorithm

A new high rate code scheme is proposed in this paper. It consists of serial concatenated recursive systematic ordinary (nonpunctured) convolutional codes with only 8 states in the trellis of the corresponding reciprocal dual codes. With a low complexity and highly parallel decoding algorithm, over additive white Gaussian noise channels, the proposed codes can achieve good bit error rate (BER) performance comparable to that of turbo codes and low density parity check (LDPC) codes. At code rate R=16/17, the overall decoding complexity of the proposed code scheme is almost half that of the LDPC codes.     

Non‐binary protograph low‐density parity‐check codes for space communications

Protograph‐based non‐binary low‐density parity‐check (LDPC) codes with ultra‐sparse parity‐check matrices are compared with binary LDPC and turbo codes (TCs) from space communication standards. It is shown that larger coding gains are achieved, outperforming the binary competitors by more than 0.3 dB on the additive white Gaussian noise channel (AWGN). In the short block length regime, the designed codes gain more than 1 dB with respect to the binary protograph LDPC codes recently proposed for the next generation up‐link standard of the Consultative Committee for Space Data Systems. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. These decoders are used to efficiently decode the best known error correcting codes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits are devised based on current mirrors, and thus, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed circuits is verified by implementing an analog MS decoder for a (32,8) LDPC code in a 0.18-mum CMOS technology. This decoder is the first reported analog MS decoder. For low signal to noise ratios where the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional floating-point discrete-time synchronous MS decoder. When data throughput is 6 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10^-3 is about 0.3 dB and power consumption is about 5 mW. This is the first time that an analog decoder has been successfully tested for an LDPC code, though a short one     

Construction of quasi‐cyclic low‐density parity‐check codes with low encoding complexity

Low encoding complexity is very important for quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes used in wireless communication systems. In this paper, a new scheme is presented to construct QC‐LDPC codes with low encoding complexity. This scheme is called two‐stage particle swarm optimization (TS‐PSO) algorithm, in which both the threshold and girth distribution of QC‐LDPC codes are considered. The proposed scheme is composed of two stages. In the first stage, we construct a binary base matrix of QC‐LDPC code with the best threshold. The matrix is constructed by combining a binary PSO algorithm and the protograph extrinsic information transfer (PEXIT) method. In the second stage, we search an exponent matrix of the QC‐LDPC code with the best girth distribution. This exponent matrix is based on the base matrix obtained in the first stage. Consequently, the parity‐check matrix of the QC‐LDPC code with the best threshold and best girth distribution are constructed. Furthermore, bit error rate performances are compared for the QC‐LDPC codes constructed by proposed scheme, the QC‐LDPC code in 802.16e standard, and the QC‐LDPC code in Tam's study. Simulation results show that the QC‐LDPC codes proposed in this study are superior to both the 802.16e code and the Tam code on the additive white Gaussian noise (AWGN) and Rayleigh channels. Moreover, proposed scheme is easily implemented, and is flexible and effective for constructing QC‐LDPC codes with low encoding complexity. Copyright © 2012 John Wiley & Sons, Ltd.     

Finite-Dimensional Bounds on Zm and Binary LDPC Codes With Belief Propagation Decoders

This paper focuses on finite-dimensional upper and lower bounds on decodable thresholds of Zopf_m and binary low-density parity-check (LDPC) codes, assuming belief propagation decoding on memoryless channels. A concrete framework is presented, admitting systematic searches for new bounds. Two noise measures are considered: the Bhattacharyya noise parameter and the soft bit value for a maximum a posteriori probability (MAP) decoder on the uncoded channel. For Zopf _m LDPC codes, an iterative m-dimensional bound is derived for m-ary-input/symmetric-output channels, which gives a sufficient stability condition for Zopf_m LDPC codes and is complemented by a matched necessary stability condition introduced herein. Applications to coded modulation and to codes with nonequiprobably distributed codewords are also discussed. For binary codes, two new lower bounds are provided for symmetric channels, including a two-dimensional iterative bound and a one-dimensional noniterative bound, the latter of which is the best known bound that is tight for binary-symmetric channels (BSCs), and is a strict improvement over the existing bound derived by the channel degradation argument. By adopting the reverse channel perspective, upper and lower bounds on the decodable Bhattacharyya noise parameter are derived for nonsymmetric channels, which coincides with the existing bound for symmetric channels     

FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.     

针对 IRA-LDPC 码类的半随机半代数结构设计

提出用半随机半代数结构的设计方法来构造IRA-LDPC码的信息位所对应的奇偶校验矩阵H d。与现有结构化LDPC码相比,所给出的H d矩阵的结构化紧凑表示阵列的独特优势在于：可使H d矩阵中每个1元素的位置坐标均能用数学表达式计算得到,不仅极大地降低了随机奇偶校验矩阵对存储资源的消耗,而且还为LDPC编解码器的低复杂度硬件实现提供了可能性。与现有工业标准中的LDPC码相比,所提出的IRA-LDPC码在误码率与信噪比的仿真性能方面也占有优势。