一个不含有传统采样保持放大器的8位100兆采样率流水线模数转换器

本文实现了一个省去传统的采样保持模块的8位100兆采样率流水线模数转换器(ADC)。与包含传统采样保持模块的相同指标的流水线ADC相比,品质因子(FoM)和面积分别降低了21%和12%。提出了一种余量增益放大器(MDAC)中运放的闭环带宽(BWclose)的模型,并通过晶体管级仿真验证了该模型。本设计采用0.18µm 1P6M CMOS混合信号工艺实现,测试结果显示,当采样率为100兆时,输入信号1MHz和80MHz对应的分辨率分别为7.43bit和6.94位,包括内置参考电压/电流源的静态功耗为23.4mW,品质因子为0.85pJ/step,面积为0.53mm2,积分非线性(INL)和差分非线性(DNL)分别为-0.99~0.76LSB,-0.49~0.56LSB。     

一个低功耗的带片上参考电压缓冲器的12位30兆采样率的CMOS流水线模数转换器

介绍了一个在0.13µm 1P8M CMOS工艺下实现的12位30兆采样率流水线模数转换器。提出了一种消除前端采样保持电路的低功耗设计方法。除了第一级之外,带双输入的两级cascode补偿的运算放大器在相邻级间共享以进一步地减小功耗。该模数转换器在5MHz的模拟输入和30.7MHz的采样速率下达到了65.3dB的SNR,75.8dB的SFDR和64.6dB的SNDR。该芯片在1.2V电源电压下消耗33.6mW。FOM达到了0.79pJ/conv step。     

一个1.2伏CMOS0.13微米工艺19.2毫瓦10位30兆采样率流水线模数转换器

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μ m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm².     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

一个没有采用校准技术的12位分辨率100兆采样率的流水线模数转换器

本文给出了一个基于0.18um CMOS工艺的12bit 100MS/s的流水线ADC。其中第一级采用了3.5比特结构以降低对电容匹配的要求,采样保持放大器、第一级和第二级均采用了自举开关以改善ADC线性度,后级采用级缩减技术节省了功耗和面积。当输入信号频率为15.5MHz、采样率为100MHz时,该ADC达到了79.8dB的SFDR和10.5bit的有效位数。芯片采用1.8V电压供电,包含输出驱动的总功耗为112mW, 芯片面积为3.51mm2 。     

一个嵌入式应用的8位300MS/s折叠内插模数转换器

本文设计了一个1.4V电源电压8位300MS/s折叠内插结构的模数转换器。该模数转换器利用0.13μm CMOS工艺实现,有效面积仅为0.6mm2,非常适合嵌入式应用。系统对低功耗进行了优化。流水线式采样开关节省了用于实现信号完整建立而增加的额外功耗。失调平均电阻阵列被置于两级折叠电路之间也是出于节省功耗的考虑。该转换器在1MHz下达到了43.4dB的信噪失真比和53.3dB的无杂散动态范围,在奈奎斯特频率输入情况下信噪失真比和无杂散动态范围分别为42.1dB和49.5dB。测试结果表明在1.4V电源250MHz采样率下功耗为34mW,FoM值为1.14pJ/转换步长。     

SFDR高于100dB的14位欠采样循环模数转换器

本文为射频标签(RFID)收发机系统设计了一个高线性,14位357 k采样率的欠采样循环模数转换器。为提高模数转换器的精度,设计中采用了有源电容误差平均(PCEA)技术。并且提出了一种改进的PCEA采样网络,可以消除两个流水级之间的串扰影响。为降低模数转换器的功耗和减小面积,设计采用了运放共享技术,并且去除了采样保持放大级。为补偿不完善的版图设计引入的误差,增加了一个附加的数字校准模块。该模数转换器由180 nm CMOS工艺流水完成,面积为0.65 mm  1.6 mm。在确保SFDR不低于90 dB的条件下,该欠采样模数转换器的输入信号频率高达15.5 MHz;在2.431 MHz输入下,峰值SFDR高达106.4 dB.     

一种10位50 MSPS CMOS流水线A/D转换器

介绍了一种CMOS流水线结构高速高精度A／D转换器，该器件具有50MHz工作频率和10位分辨率。设计采用双采样技术，提高了有效采样率；由于运用了冗余数字校正技术，可以采用低功耗的动态比较器。对转换器的单元结构进行了优化，并对主要电路进行了分析。     

带输入缓冲电路的12位200兆流水线模数转换器

在12 bit 200 M采样率的模数转换电路(ADC)中实现了片内CMOS输入缓冲电路,输入缓冲电路采用源极跟随器电路构架。通过分析源极跟随器的非线性特点,在输入缓冲电路中加入高通滤波电路、复制电容电路等方式,有效提高了输入缓冲电路的线性度。将该输入缓冲电路用于无数字校准的12 bit 200 M采样率的流水线型模数转换电路(ADC)中,用台积电0.18μm CMOS工艺条件下流片验证,当采样时钟为200 MHz、输入信号频率为10 MHz、振幅为1.4 V_(pp)时其失真噪声比(SNDR)为63.5 dB,无杂散动态范围(SFDR)为78.6 dBc,ADC总体功耗为500 mW。     

A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm IP6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.     

一个71mW 8位125MHz A/D转换器

介绍了工作在1.8V的8位125MHz流水线A/D转换器.采用了低功耗的增益自举单级折叠级联运放,器件尺寸逐级减小进一步优化功耗.为消除不匹配造成的相位遗漏与重叠,每级均有独立的双相不交叠时钟发生电路,并由一全局的时钟树驱动.输入频率为62MHz的信号,以125MHz时钟采样,可获得49.5dB(7.9位有效精度)的信号与噪声及谐波失真比(SNDR),功耗仅为71mW.电路用0.18μm CMOS 工艺实现,面积为0.45mm2.     

一个71mW 8位125MHz A/D转换器

介绍了工作在1.8V的8位12 5 MHz流水线A/ D转换器.采用了低功耗的增益自举单级折叠级联运放,器件尺寸逐级减小进一步优化功耗.为消除不匹配造成的相位遗漏与重叠,每级均有独立的双相不交叠时钟发生电路,并由一全局的时钟树驱动.输入频率为6 2 MHz的信号,以12 5 MHz时钟采样,可获得4 9.5 d B(7.9位有效精度)的信号与噪声及谐波失真比(SNDR) ,功耗仅为71m W.电路用0 .18μm CMOS工艺实现,面积为0 .4 5 m m2 .     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique

This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8×1.4 mm² in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200 MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4 MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49 dB–70.71 dB while consuming of 112 mW at a supply voltage of 1.1 V.     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

一款带8选1MUX的14位2.5GS/s D/A转换器

本文介绍了一款带8选1MUX的14位2.5GS/s D/A转换器。该转换器采用了“5+9”分段PMOS电流舵结构,偏置电路保证PMOS电流源阵列能够在PVT（温度、电源电压、工艺角）变化的条件下获得较大的输出阻抗。高速8to1 mux电路采用了3级结构,采用恰当的数据选择时序,提高了数据合成的可靠性。D/A转换器输入数据的高5位译码器中加入了DEM功能改善了D/A转换器模拟输出的动态性能。本文所述的带8选1MUX功能的14位2.5GS/s D/A转换器内嵌在一款高性能DDS电路中,流片的实测结果显示在时钟2.5GHz下, MUX和D/A转换器工作正常,输出信号在1GHz带宽范围内,SFDR> 40dB。与目前国际上已发表的非模拟重采样结构的D/A转换器（即没有采用“归零”或“四开关”这些模拟重采样结构）相比,本文介绍的D/A转换器具有较高的时钟频率（2.5GHz）和较好的高频SFDR性能(>40dB, up to 1GHz)。     

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low oversampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate, The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.