计算机随机存储器

随机存储器（RAM）也叫主内存,俗称内存（Memory）,其广意指计算机中的各种内存,而RAM只是其中的一种。RAM的具体组件称为内存条,它的技术、性能及容量等随着CPU的更新而不断升级与提高,以适应更快更好的CPU运行的需要。RAM一般分为两类：动态RAM（DRAM）及静态RAM（SRAM）,由于SRAM的读写速度远快于DRAM,所以PC中SRAM大都作为高速缓存（Cache）使用,DRAM则作为普通的内存和显示内存使用。RAM的特点是可以随时存取数据,但是一旦断电,保存在其中的数据就会全都丢失。衡量DRAM性能的重要指标是RAM芯片的存…     

基于MSP430单片机的现场数据实时采集系统

本文根据现场数据采集系统的设计原则,采用片内自带A/D转换模块及大容量数据RAM且微功耗性能突出的MSP430F149单片机,并结合大容量串行FLASH数据存储器,详细阐述了能满足现场应用环境的大容量数据实时采集系统的设计思路和具体实现方法.     

基于SRAM和DRAM结构的大容量FIFO的设计与实现

分别基于Hynix公司的SRAM HY64UD16322A和DRAM HY57V281620E,介绍了采用两种不同的RAM结构,通过CPLD来设计并实现大容量FIFO的方法.     

海力士半导体DRAM产品获得ISi的Z-RAM存储技术授权

Z-RAM高密度存储知识产权（IP）开发商Innovative Silicon Inc（ISi），与海力士（Hynix）半导体有限公司8月13日宣布：海力士已经同意在其动态随机存储器（DRAM）芯片中采用ISi的Z－RAM技术。采用Z－RAM的DRAM将使用一种单晶体管位单元，来替代多个晶体管和电容器的组合，这代表了自上世纪70年代初发明DRAM来，基本DRAM位单元实现了首次变革。[第一段]     

逻辑分析仪在SDRAM测量中的应用

1．引言 在嵌入式系统中,经常要用到大容量的随机存储器（RAM）来运行程序或存储数据,SDRAM（Synchronous DRAM,同步动态随机存储器）即是其中之一,凭借着低廉的价格、大容量、与系统总线速率同步等优势,应用非常广泛,特别适用于图像处理、高速数据采集等场合。由于SDRAM的操作时序相对比较复杂,接口不能直接与大部分微处理器的存储器接口相连接,     

DDR SDRAM引领内存新风采

回顾20多年前，DRAM（动态读写存储器）之所以被采用为电脑存储的重要因素，其实是DRAM的性能及频宽能满足当时CPU需求所致。之后，由于CPU及系统性能的提升，DRAM的技术由Fast Page Mode（快速页面模式）DRAM，EDO DRAM（扩展数据输出）发展到同频式的SDRAM（静态随机存取存储器），PCB内存条在这个过程中其速度也由PC66，PC100提升到几年前才开始盛行的PCB内存条，从这个过程可以清楚地看出成本一直是主宰新技术取代旧技术的主要原因，而频宽则是相对主要的关键。     

MCS96系列单片机扩展大容量FLASHRAM的改进

目前在单片机的应用开发中，FASHRAM使用非常普遍，本文根据MCS96系列单片机的一种大容量的外部RAM扩展技术思想，针对扩展大空量FLASHRAM给出了具体的改进措施。     

基于FPGA的DDR内存条的控制

随着数据存储量的日益加大以及存储速度的加快,大容量的高速存储变得越来越重要。内存条既能满足大容量的存储又能满足读写速度快的要求,这样使得对内存条控制的应用越来越广泛。首先介绍了内存条的工作原理,内存条电路设计的注意事项,以及如何使用FPGA实现对DDR内存条的控制,最后给出控制的仿真波形。     

基于SIMM内存条的大容量图像帧存储器设计

图像帧存储器是数字图像系统的核心部件,它具有存储容量大和工作刷新速度快的特点。本文分析了由DRAM构成的图像帧存储器中数据总线和地址总线的设计特点,介绍了采用廉价的微机用SIMM内存条来设计大容量图像帧存储器的方法。进一步提出通过合理安排地址可以充分利用SIMM内存条的额定存储容量,实现了既经济又高效的图像帧存储器。     

DRAM技术的发展动态

概述动态读写存储器DRAM（DmnamicRandomAccessMemory）是利用MOS存储单元分布电容上的电荷来存储数据位，由于电容电荷会泄漏，为了保持信息不丢失，DRAM需要不断周期性地对其刷新。这种结构的存储单元所需要的MOS管较少，因此DRAM的集成度高、功耗小，同时每位的价格最低。DRAM一般用于大容量系统中。DRAM的发展方向有两个一是高集成度、大容量、低成本；二是高速度、专用化。1996年市场上以4位和16位DRAM芯片为主，1997年以16M位为主，1998年64M位开始大量上市，同年市场占有率达到52％，16MDRAM的市场占有率为45％。今…     

Hidden double data transfer scheme for MDL design [merged DRAMlogic]

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 μm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory     

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs     

Single Chip Dual–Issue RISC Processor for Real–Time MPEG–2 Software Decoding

A single chip system for real–time MPEG–2 decoding can be created by integrating a general purpose dual–issue RISC processor, with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32KB instruction RAM; and a 32KB data RAM. The VLD hardware performs Huffman decoding on the input data. The block loader performs the half–sample prediction for motion compensation and acts as a direct memory access (DMA) controller for the RISC processor by transferring data between an external 2MB DRAM and the internall 32 KB data RAM. The dual-issue RISC processor, running at 250MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra video blocks are decoded in less than 800 cycles, leading to a single-chip, real-time MPEG-2 decoding system.     

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integratedmedia chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm² /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule     

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.     

A 0.9-V microcontroller for portable applications

A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers     

A fast 256K DRAM designed for a wide range of applications

A 256K DRAM designed for a variety of organizations and operation modes is described. The chip may be organized as 64K/spl times/4, 128K/spl times/2, or 256K/spl times/1. Four data I/O buffers are selectable by gate signals. Besides the standard RAM mode, it may be operated in the page mode, in the parallel or serial buffer mode, and in a combination of page and serial buffer modes. With these options, the design covers a wide range of applications. RAS/CAS access times are 80.55 ns. In the combined page and serial buffer mode, a data rate of up to 50 MHz is possible. The chip is built in metal-gate n-channel technology with 2-/spl mu/m minimum line width and two metal interconnection planes.     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.