Ultrafast compact 32-bit CMOS adders in multiple-output dominologic

A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5× and 1.7× over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9-μm two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25°C with V_DD+5.0 V     

A comparative study on performance and reliability of 32-bit binary adders

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.     

Evaluation of two-summand adders implemented in ECDL CMOSdifferential logic

Four different adders were implemented using a CMOS differential logic, enable/disable differential CMOS logic (ECDL). The authors discuss the design and implementation of several common addition algorithms using ECDL. These adders have the self-timed characteristic. Comparisons are made among these algorithms in terms of delay and area. The actual implementation was done with MOSIS 3-μm scalable process. Evaluations are performed in terms of area and delay. One conclusion that can be made is that the carry-skip adder seems to have the best speed/area combined performance. A first-order modeling method is used to estimate the area and speed of different implementations     

A high-performance CMOS 32-bit parallel CRC engine

Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-μm three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register     

Power-delay characteristics of CMOS adders

An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic design of an adder to improve its power-delay product are identified. An effective way of improving the speed of a circuit is by transistor sizing which unfortunately increases power dissipation to a large extent. It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product. Perflex, an in-house performance driven layout generator, is used to systematically generate sized layouts     

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.     

A 32-bit carry lookahead adder using dual-path all-N logic

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.     

Low-power design techniques for high-performance CMOS adders

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 μm CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V     

A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller

The SOC implementation of a capacitive fingerprint sensor, which embeds the 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of a 160/spl times/192 pixel array with a sensor detection circuit and the embedded 32-bit RISC microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 180% more than conventional detection circuit does and minimizes any electrostatic discharge influence by applying an effective isolation structure. The test chip was fabricated on a 0.35-/spl mu/m standard CMOS 1-poly 4-metal process.     

Power-delay product minimization in high-performance 64-bit carry-select adders

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.     

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25-μm CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V     

3.3-V BiCMOS current-mode logic circuits for high-speed adders

New high-speed BiCMOS current mode logic (BCML) circuits for fast carry propagation and generation are described. These circuits are suitable for reduced supply voltage of 3.3-V. A 32-b BiCMOS carry select adder (CSA) is designed using 0.5-μm BiCMOS technology. The BCML circuits are used for the correct carry path for high-speed operation while the rest of the adder is implemented in CMOS to achieve high density and low power dissipation. Simulation results show that the BiCMOS CSA outperforms emitter coupled logic (ECL) and CMOS adders     

A 32-bit microprocessor for Smalltalk

SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.     

A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-$muhbox m$standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2$muhbox m^2$three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external$hboxI^2hboxC$master device such as universal$hboxI^2hboxC$serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9$hbox mm^2$. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications.     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

一种32位MCU的FPGA验证平台

随着应用的复杂化和多样化,微控制器(MCU)设计规模急剧增大,性能要求越来越高。为缩短芯片验证时间,提高验证效率,采用FPGA原型验证平台是一个有效的方法。通过建立基于FPGA的高性能原型验证系统,可及时发现芯片设计中的错误和不足,进而缩短MCU芯片研发周期。以一款通用MCU为研究对象,通过修改时钟系统,替换存储器和综合布局布线设计FPGA验证平台,并利用该平台进行软硬件协同验证,为该芯片的验证工作提供了高效有力的支撑。     

基于选择进位32位加法器的硬件电路实现

为了缩短加法电路运行时间,提高FPGA运行效率,利用选择进位算法和差额分组算法用硬件电路实现32位加法器,差额分组中的加法单元是利用一种改进的超前进位算法实现,选择进位算法可使不同的分组单元并行运算,利用低位的运算结果选择高位的进位为1或者进位为零的运算结果,节省了进位选择等待的时间,最后利用XILINX进行时序仿真,在FPGA上进行验证,可稳定运行在高达50兆的频率,理论分析与计算机仿真表明该算法切实可行、有效并且易于实现。     

32位微控制器——嵌入式市场的助推剂

下面的话听起来可能让人觉得荒谬:要进入微控制器市场,你必须事实上已经入了这一行.围绕着每一种类型的微控制器的残酷竞争已经把价格拉得如此之低,以至于如果你需要获取外设与各种存储器的许可或者购买这些构成MCU价格的主要组成部分的模块的话,你就无利可图.达还不够:你必须向你的客户提供大量的MCU结构选项.     

High-speed 32-bit buses for forward-looking computers

The features offered by current high-performance 32-bit system buses are examined. They allow multiprocessing, scalability, block transfers to RAM, cache coherence, and autoconfiguration (the ability to poll boards connected to them, identify the boards, and adjust the software interface accordingly). The factors that need to be taken into account when designing these buses are considered, and their performance and limitations are discussed     

Threshold logic circuit design of parallel adders using resonanttunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed