DSP芯片技术实验的探索与开发

介绍了数字信号处理器(DSPs)的结构及技术特性，系统地总结了基于TI公司DSP芯片的JTAG仿真开发系统的软件开发工具和系统集成、调试工具，详细地分析了不同的DSP实验的硬件开发环境，并具体地探讨了一般的DSP实验项目(熟悉CC，存储器寻址测试，中断测试，D／A转换，FIR，FTT等)以及针对电信、自动化等专业的专门DSP实验项目(DSP直流电机调速系统扩展实验板DSP语音回放系统扩展实验板等)的开发方案。     

基于TMS320C5400平台的μC/OS-Ⅱ的研究

为了缩短DSP应用程序开发的时间、增DSP软件的模块化以及更充分地利用DSP计算能力，有必要将RTOS引入到DSP应用程序的开发中。本文分析引入RTOS的作用和优势，在TIC5400DSK平台上移植了μC／OS-Ⅱ，试探性地利用语音编解码应用作为实例讨论其实现细节，并通过具体实验把基于RTOS的开发方法与传统编程方法进行了比较。     

H．264编解码器在C6416DSP上的实现与优化

H．264是由ITU—T和ISO联合制定的新一代视频编码标准，有着码率低，质量高的特点。C64x系列DSP是目前TI公司推出的性能最高的定点DSP，NVDK(Network Video Development Kit)是其很好的仿真平台。本文介绍了H．264基于TI C6416DSP的优化与实现方法，通过仿真实验，编解码器在Qcif格式下达到实时编解码效果，能够满足实时通信要求。本文介绍了H．264在DSP上实现和优化的手段，最后给出实验结果。     

基于TMS320C5420的2FSK设计与实现

基于DSP的软件无线电技术在通信领域得到了广泛的应用。我们使用TI公司的TMS320C5420 DSP芯片成功设计了一种兼容2FSK，DPSK，QAM等多种调制解调方式的JH5001通信原理实验系统，在系统硬件不变的情况下只要修改DSP的软件处理部分就能实现无线参数的改变和增加新的功能。详细介绍了用DSP实现2FSK调制解调的算法，并就解调中所应用的数字滤波器做了具体分析。     

基于USB2.0的高速数据通信接口设计

随着数字信号处理速度的提高，传统的串口，并口已不能满足主机与DSP之间的高速数据传输要求，因而，介绍了一种基于TMS320C5402DSP和CY7C68013的UStE．0系统。利用FPGA进行I／O口的扩展，克服了I／O口功能弱的缺点，提高了DSP的控制能力。实验表明，该系统具有速度快，可靠性高的优点。     

基于TMS320F2812的感应电机直接转矩控制实现

本文介绍了基于开关表格的感应电机直接转矩控制（ST-DTC），并且提出了以TMS320F2812 DSP为核心的实验控制系统，通过实验验证了ST-DTC控制方案的可行性。     

DSP应用教学的探索和实践

文章介绍了TI公司DSP的应用教学的特点和具体实施。说明了DSP应用教学主要是对学生进行工程应用教育，培养学生自学能力和实践能力，突出了实践教学在DSP应用教学中的重要地位。把DSP应用教学分为初步教学、基础教学和提高教学三个阶段，从验证性实验、开发性实验到综合性实验，逐步培养学生的DSP应用能力。     

基于DSP 器件的ACELP 语音编码算法的实现􀀂

本文研究了语音编码中代数码激励线性预测（ACELP）的算法，并给出了其基于数字信号处理（DSP）的实现方法。首先本文介绍了ACELP编码的基本原理，然后给出了线性预测（LP）系数与线谱对（LSP）之间的转化关系。最后给出了基于DSP实现的ACELP编码的框图。实验结果证明，该方法可以得到良好的话音质量输出。     

基于DSP的分布式光纤测温系统及高速数据采集与处理

提出了一种基于数字信号处理器(DSP)的分布式光纤测温系统，系统以DSP为核心，以并行高速流水线式ADC，FIFO和CPLD为主体实现对光纤温度传感器输出信号的高速数据采集与处理，其采样速率可达100MSPS。全面介绍了该系统的原理应实现过程。并讨论了实验结果。     

兴夏举办’99国际DSP技术及新产品研讨会

近日，世界可编程DSP系统的领先厂商Spectrum公司和公司的系统集成商──兴夏机电设备有限公司在北京举办了’99国际DSP技术及新产品研讨会。研讨会就SHARC和C6000的体系结构及性能作了对比、并现场演示了并行DSP系统的软件开发工具SpectrumAPEX，展示了最新推出的基于数字无线电的产品──一系列多平台多DSP的数字无线电模块，它们可构成多种数字无线电系统。该系统主要支持的平台有：PCI、VME、VXI和CompactPCI。其中，基于PCI单通道数字无线电系统可用于频谱监测、研究和实验系统等，基于VME和CompactPCI多通道数字无…     

当代DSP及其在现代通信应用中面临的挑战

本文首先从数字信号处理算法的运算特点出发,讨论了数字信号处理运算对DSP硬件性能的要求,当代DSP面临的现代通信的挑战,以及在硬件体系结构上所采取的相应措施,并介绍了DSP在通信中的应用及发展趋势。     

Low power design for DSP: methodologies and techniques

Power dissipation is becoming a limiting factor in the realization of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design techniques are now emerging. This paper provides an overview of the techniques and methodologies that have emerged in the past few years for DSP system design. These include techniques for minimizing power at architectural and algorithmic levels including DSP programming issues. In addition, the paper indicates some potential design directions.     

From Bit Level Systolic Arrays to HDTV Processor Chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on ”algorithmic engineering” and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology.     

Architectural Synthesis of Digital Signal Processing Algorithms Using “IRIS”

In this paper, we present the IRIS architectural synthesis system for high-performance digital signal processing. This tool allows non-specialists to automatically derive VLSI circuit architectures from high-level, algorithmic representations, and provides a quick route to silicon implementation. By incorporating a novel synthesis methodology, called the Modular Design Procedure, within the IRIS system, parameterised models of complex and innovative DSP hardware can be derived and automatically assembled to create new DSP systems. The nature of this synthesis methodology is such that designers can explore a large range of architectural alternatives, whilst considering all the architectural implications of using specific hardware to realise the circuit. The applicability of IRIS is demonstrated using the design examples of a second order Infinite Impulse Response filter and a one-dimensional Discrete Cosine Transform circuit.     

Soft digital signal processing

In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delay imbalance" are employed. A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60-81% reduction in energy dissipation for filter bandwidths up to 0.5 π (where 2 π corresponds to the sampling frequency f_s) over that achieved via conventional architecture and voltage scaling, with a maximum of 0.5-dB degradation in the output signal-to-noise ratio (SNR_o). It is also shown that the proposed algorithmic noise-tolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10^-3 due to deep submicron (DSM) noise     

一种高速DSP中延迟优化的乘累加单元的设计与实现

乘累加单元是任何数字信号处理器(DSP)数据通路中的一个关键部分.多年来,硬件工程师们一直倾注于其优化与改进.本文描述了一种速度优化的乘累加单元的设计与实现.本文的乘累加单元是为一种高速VLIW结构的DSP核设计,能够进行16×16 40的无符号和带符号的二进制补码操作.在关键路径延迟上,本文的乘累加单元比其他任何使用相同或不同算数技术实现的乘累加单元都更优.本文的乘累加单元已成功使用于synopsys的工具,并与synopsys的Design Ware库中相同位宽的乘累加单元比较.比较结果表明,本文的乘累加单元比Design Ware库中的任何其他实现都要快,适合于在需要高吞吐率的DSP核中使用.注意:比较是在Design compiler中使用相同属性和开关下进行的.     

Reconfigurable Testbed for Interference Cancellation in DS-CDMA Systems

Interference cancellation techniques fordirect-sequence code division multiple access (DS-CDMA)systems have the potential to provide significantcapacity gains over conventional matched filterreceivers. The complexity of the signal processingalgorithms for interference cancellation often requiresprocessing speeds that are beyond that of currentdigital signal processor (DSP) technology. In thispaper, we show that this difficulty can be overcome bypartitioning the algorithmic functionality into two coretechnologies (field programmable gate arrays [FPGA] andDSP devices) based on processing speed requirements. We give implementation proofs via a testbedthat allows a dynamic reconfiguration among constituentreceivers being considered. Experimental results on theperformance of the receivers are presented.     

基于DSP的网络接口电路设计

DSP体积小、成本低、易于产品化、可靠性高、易扩展、能方便地实现多机分布式并行处理,所以在航空航天、工业控制、科学研究等方面获得了越来越多的应用。以DSP为核心的复杂计算和控制的嵌入式系统设计思路逐步成为电子设备工程师的首选。因此基于DSP和网卡设计了一个网络传输系统,给出了系统整体电路设计和相应的软件程序。经实验表明,该系统能成功地发射和接收信号。