共查询到18条相似文献,搜索用时 121 毫秒
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基于国内的CMOS技术和EDA工具以及全定制的设计方法 ,采用无锡华晶上华 (CSMC HJ) 0 6 μmCMOS技术实现了可工作于 15 5Mb/s、6 2 2Mb/s的激光驱动器 .该激光驱动器在 5 0Ω负载上输出电流摆幅从 0到 5 0mA可调 .在输出级 3V直流偏置时最大输出电压摆幅可达 2 5Vpp.输出电压脉冲的上升、下降时间分别小于 471ps和 44 4ps.四个工作速率下均方根抖动都小于 30ps.电路在 5V单电源供电时功耗小于 410mW .芯片测试结果表明 ,该激光驱动器达到了世界同类集成电路的水平 . 相似文献
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基于国内的CMOS技术和EDA工具以及全定制的设计方法,采用无锡华晶上华(CSMC-HJ)0.6μm CMOS技术实现了可工作于155Mb/s、622Mb/s的激光驱动器.该激光驱动器在50Ω负载上输出电流摆幅从0到50mA可调.在输出级3V直流偏置时最大输出电压摆幅可达2.5Vpp.输出电压脉冲的上升、下降时间分别小于471ps和444ps.四个工作速率下均方根抖动都小于30ps.电路在5V单电源供电时功耗小于410mW.芯片测试结果表明,该激光驱动器达到了世界同类集成电路的水平. 相似文献
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0.6可用于光纤用户网的0.6μmCMOS激光驱动器 总被引:3,自引:0,他引:3
基于国内的CMOS技术和EDA工具以及全定制的设计方法,采用无锡华晶上华(CSMC-HJ)0.6μm CMOS技术实现了可工作于155Mb/s、622Mb/s的激光驱动器.该激光驱动器在50Ω负载上输出电流摆幅从0到50mA可调.在输出级3V直流偏置时最大输出电压摆幅可达2.5Vpp.输出电压脉冲的上升、下降时间分别小于471ps和444ps.四个工作速率下均方根抖动都小于30ps.电路在5V单电源供电时功耗小于410mW.芯片测试结果表明,该激光驱动器达到了世界同类集成电路的水平. 相似文献
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恒电压增益的低电压Rail—to—Rail运算放大器 总被引:3,自引:0,他引:3
基于 Alcatel的 0 .3 5μm标准 CMOS工艺 (VT=0 .6 5 V) ,模拟实现了工作电压低达 1 .8V、电压增益偏差仅为 3 % (整个输入共模偏置电压范围内 )的运算放大器 ;电路的设计也避免了差分输入对中 PMOS管和 NMOS管的 W/L的严格匹配 ,增强了电路对工艺的坚固性。对输入差分对偏置电流的控制电路、差分输入对的有源负载和 AB类 Rail- to- Rail输出级进行了整体考虑 ,确保电压增益恒定的新型结构 ,使该运放在 2 V电源电压下 ,电压增益达到 80 d B(1 0 kΩ 电阻和 1 0p F电容并联负载 ) ,单位增益带宽为 1 2 MHz,相位裕量 72° 相似文献
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高速LVDS收发芯片的设计 总被引:1,自引:0,他引:1
本文设计了一种新型低功耗LVDS(Low Voltage Differential Signaling)收发电路。对比于传统的发射电路,本次设计片内集成了共模反馈控制,同时为了提高该电路的工作速度,还设计了一个电流补偿电路来改善输出的时延特性,使得其最高工作速率能达到622Mb/s;而在接收电路方面,该设计解决了传统LVDS接收电路在共模信号输入范围大时性能不能满足要求的问题。另外,此接收电路还支持失效保护功能。该收发一体芯片已采用华润上华科技有限公司(CSMC)0.5µm CMOS工艺流片。测试结果表明,发送电路的最高工作速率超过622Mb/s,5V电源电压下静态工作电流仅为6mA。接收电路在宽的共模输入电压范围(0.1~2.4V)及低达100mV的差模输入信号条件下均能稳定工作。在400 Mb/s的最高工作频率下,静态工作电流仅为1.2mA。芯片满足TIA/EIA-644-A标准,可以应用于LVDS收发系统。 相似文献
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一种用于Bluetooth发接器的倍频式VCO 总被引:2,自引:0,他引:2
介绍了一种适用于 Bluetooth发接器的 ,可以单片集成的倍频式压控振荡器 ( VCO)。这种 VCO由两部分组成 ,主 VCO的振荡频率是所需本振频率的一半 ,然后采用“注入锁频”原理对主 VCO的振荡频率进行倍频以产生本振信号。主 VCO和倍频电路都使用了片上集成螺旋电感 ,调谐用的变容元件使用 PMOS晶体管实现。经过版图设计和后仿真 ,在 TSMC0 .35 μm数字 COMS工艺 ,3.3V电源电压下 ,该 VCO在 2 .4GHz中心频率附近可以达到的相位噪声指标为 -1 2 5 d Bc/Hz( 60 0 k Hz) ,在输出摆幅为 60 0 m Vp- p时 ,功耗为 2 2 m W。 相似文献
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设计了一款单电流源模式低电压差分信号(LVDS)驱动器.采用反馈控制电路,以降低工艺、电压和温度变化引起的输出电平波动,电路稳定在规定的范围内.采用0.18 μm CMOS工艺设计,仿真结果表明,驱动器工作速率可以达到660 Mb/s,差分输出信号摆幅为320 mV. 相似文献
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High-gain SiGe transimpedance amplifier array for a 12/spl times/10 Gb/s parallel optical-fiber link
Schild A. Rein H.-M. Mullrich J. Altenhain L. Blank J. Schrodinger K. 《Solid-State Circuits, IEEE Journal of》2003,38(1):4-12
A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 /spl mu/A/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12/spl times/10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools. 相似文献
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Chorng-Kuang Wang Po-Chiun Huang Chen-Yi Huang 《Solid-State Circuits, IEEE Journal of》1996,31(8):1197-1200
This paper presents a Synchronous Optical NETwork (SONET) OC-3 155.52 Mb/s limiting amplifier, which is implemented in a 1.0 μm double-poly double-metal N-well BiCMOS technology. Composed of amplifier cells, a slicer, an output driver, and offset cancellation circuits, this limiting amplifier allows an input dynamic range of 36 dB (6 mVpp~400 mVpp) and provides a constant output 1 V pp across a 50 Ω load for long-haul 40 km application. The active area of this limiting amplifier is 0.8 mm×3.0 mm. It consumes 130 mW from a single -5 V supply voltage 相似文献
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《Solid-State Circuits, IEEE Journal of》1987,22(4):504-511
A monolithic integrated high-gain limiting amplifier for future optical-fiber receivers is described. It is characterized by the following features: high insertion-voltage gain (maximum 54 dB); high input dynamic range (about 52 dB) at constant output-voltage swing (400 mV/SUB p-p/); high operating speed (up to at least 4 Gb/s); low power dissipation (350 mW at 50-/spl Omega/ load); standard supply voltage (5 V); 50-/spl Omega/ output buffer; one-chip solution; and small fabrication costs by use of a 2-/spl mu/m standard bipolar technology without needing polysilicon self-aligning processes. The good values of operating speed and power consumption, which the authors believe has until now not nearly been achieved by other comparable bipolar amplifier ICs, are a result of careful circuit design and optimization. The amplifier was extended to a high-sensitivity (amplitude and time) decision circuit operating at up to 4.0 Gb/s by adding a high-speed master-slave D-flip-flop IC fabricated with the same technology. 相似文献
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采用SMIC0.18μm 1P6M混合信号CMOS工艺设计了10Gb/s限幅放大器。该放大器采用了带有级间反馈的三阶有源负反馈放大电路。在不使用无源电感的情况下,得到了足够的带宽以及频率响应平坦度。后仿真结果表明,该电路能够工作在10Gb/s速率上。小信号增益为46.25dB,-3dB带宽为9.16GHz,最小差分输入电压摆幅为10mV。在50Ω片外负载上输出的摆幅为760mV。该电路采用1.8V电源供电,功耗为183mW。核心面积500μm×250μm。 相似文献
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ZHANGYaqi ZHAOHongmin 《半导体光子学与技术》1999,5(1):51-57
A broadband amplifer with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study.Making use of the basic amplifier cells.a main amplifier IC for optical-fiber receivers is deliberated.By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range.They are maximum voltage gain of 42 dB,ths bandwidth of 730 MHz,the input signal(Vp-0)range from 5 mV to 1V,the output amplitude about 1V,the dynamic range of 46 dB.The designed circuit containing no inductance and large caacitance will be convenient for realizing integration.A monolithic integrated design of 622Mb/s main amplifier is completed. 相似文献
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《Solid-State Circuits, IEEE Journal of》2006,41(9):2067-2076
A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18$muhbox m$ SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel$2^7-1$ PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p. 相似文献
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High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links 总被引:1,自引:0,他引:1
Mullrich J. Thurner H. Mullner E. Jensen J.F. Stanchina W.E. Kardos M. Rein H.-M. 《Solid-State Circuits, IEEE Journal of》2000,35(9):1260-1265
A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 Vpp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V 相似文献