计算机软件基础数据结构之算法分析

计算机软件的基础数据结构，主要负责讲解计算机内信息的寄存方式、集合和整理，通常是与算法密不可分的。算法是能够被计算机分辨和识别的指令，指令的内容就是通过计算机软件基础数据结构来进行寄存的信息。数据结构的算法分析，可以使计算机处理比较复杂的难题，提高了效率，本文对计算机基础数据结构的算法进行了分析。     

数学算法对计算机编程优化策略

本文针对数学算法和计算机编程基础内容,以及两者之间相关性展开分析,结合数学算法在计算机编程中应用的目的和意义,通过研究数学算法在C语言运用、数据结设计、建立数学模型、对象语言、编程结构中的具体应用,其目的在于提升数学算法应用效果,优化计算机编程内容。     

JEM-1200EX透射电镜透镜电路分析及故障检查方法

本文对透射电镜JEM-1200EX透镜系统的参考电压,数模转换(DAC),跟随器,比例放大,功放,反馈,取样显示和故障检查方法进行了分析,讨论。 JEM-1200EX电镜的透镜部份均由计算机控制。从电镜操作面板上将执行指令,通过计算机的输入接口,送入计算机,然后根据指令的要求,计算机按地址从内存中读出所需的数据。通过输出接口经母线将数据送入缓冲记存器中(DAC)数模转换,功放,流程图如1。该电镜的透镜电流变化的范围已由厂家以二进制码的形式存储在计算机的只读存储器中(ROM)。根据操作要求,计算机按地址取数据,通过母线将数据输送到接口(1TF),然后进入缓冲记存器。     

基于C/S结构的计算机组成原理模型机仿真系统

提出了一种基于C/S结构的计算机组成原理模型机仿真系统,服务器端仿真实现模型机的硬件逻辑;客户端采用WPF仿真实现模型机的各个计算机部件,能够让学生自行编辑指令和设计微程序,可以将执行指令的命令发送至服务器端,根据服务器端返回的数据实时动态显示指令执行过程中数据的变化。     

LS SIMD计算机的并行技术

文章主要讨论了LSSIMD计算机中所采用的并行技术数据并行技术、三级指令流水线并行技术与三组指令并行执行技术。     

一种基于GCC的VLIW编译器指令调度算法

指令调度是编译优化过程中的重要技术。对于VLIW机器来讲，由于机器性能与编译器的设计和实现有很大的关系，指令调度就显得尤为重要。指令调度是在保证语义正确的前提下，改变指令执行的顺序，以提高指令级并行的程度。文章在一个DSP芯片C编译器上的工作基础上，介绍了一种行之有效的指令调度算法，并分析了算法的正确性。     

基于Web的大型数据预览系统的设计与改进

由于传统的大型数据预览系统无法有效掌控复杂多变的大型数据,数据预览效果差。因此,提出基于Web的大型数据预览系统,该系统由大型数据预览模块、大型数据监管模块、统计报表模块和计算机组成。大型数据预览模块由浏览器、服务器和大型数据库组成,用户选择所需查询数据的标题后,浏览器会将该标题的指令传输给服务器,服务器根据指令进行大型数据的压缩处理,并反馈到浏览器中进行显示。大型数据监管模块可将大型数据预览模块中抽象的大型数据变换为直观图像进行调整,调整后的图像会被转换成大型数据格式并传输给统计报表模块,统计报表模块将整个系统的大型数据汇总成各类报表并显示在计算机上。系统的软件设计部分给出了大型数据节点分布的调节算法和流程,以保证Web大型数据预览系统的正常运行。实验结果表明所设计的系统具有较高的稳定性和准确性。     

基于循环队列的图像数据动态码本的数据结构研究

根据图像数据相关性及计算机体系结构中内存和cache的作用，在码本数据库和被匹配的码字之间建立一个存储结构，这个存储结构用来存储最近使用频率较高的码字。在本存储结构中引入了循环队列的概念，因而关于本存储结构的许多算法都体现了队列先进先出的特点，正好和相邻图像数据的相关性相吻合。所以这个数据结构解决了输出码字和搜索最佳码字之间的速度差异。     

AES加密算法在远程控制系统中的应用

在远程控制系统中,大量的数据以明文形式传输。为了解决远程控制系统中的数据安全问题,需要对数据进行加密之后再传输。分析了数据加密的方式和加密粒度,选择了高安全性能的AES算法作为加密算法。讨论了AES加密算法的结构和几种变换的过程,并根据实际应用设计了加密/解密模块的软件和硬件实现。采用C++语言实现可传输加密数据的上位机客户端和远程服务器,通过以太网和远程服务器控制单片机,单片机接收指令并通过硬件解密指令执行指令。实验结果表明,此实现方法较好地消除了安全隐患,同时又易于实现,为AES算法在嵌入式中的应用提供参考。     

基于动态优先权的无线参数下发方法

提出了一种基于动态优先权的LTE无线参数下发算法,该算法综合考虑多网共存网络优化的优先级要求以及异系统无线参数调整方案的相关性,通过预测指令下发时间,根据动态优先权和分组的应对复杂的无线指令调整需求。该方法可以提高网络优化的效率,降低优化工作对操作人员专业程度和优化经验的依赖性。     

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC

For mobile intelligent robot applications, an 81.6 GOPS object recognition processor is implemented. Based on an analysis of the target application, the chip architecture and hardware features are decided. The proposed processor aims to support both task-level and data-level parallelism. Ten processing elements are integrated for the task-level parallelism and single instruction multiple data (SIMD) instruction is added to exploit the data-level parallelism. The Memory-Centric network-on-chip7 (NoC) is proposed to support efficient pipelined task execution using the ten processing elements. It also provides coherence and consistency schemes tailored for 1-to-N and M-to-1 data transactions in a task-level pipeline. For further performance gain, the visual image processing memory is also implemented. The chip is fabricated in a 0.18- $mu$m CMOS technology and computes the key-point localization stage of the SIFT object recognition twice faster than the 2.3 GHz Core 2 Duo processor.      

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design     

Application of instruction analysis/scheduling techniques toresource allocation of superscalar processors

This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional-unit usage and the microoperation level parallelism (MLP), which together determine the proper functional-unit allocation for superscalar microprocessors, such as the x86 microprocessors. The proposed techniques fit in the early design exploration phase in which the trace or microarchitecture simulator has not been available. The techniques have been applied to analyze several popular Windows95 applications such as Word, Excel, Communicator, etc., for their MLP and distribution of functional-unit usage. The results are used to evaluate the resource allocation of several existing x86 superscalar microprocessors and suggest future extension     

Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism

As technology scaling reduces pace and energy efficiency becomes a new important design constraint, superscalar processor designs are reaching their performance limits due to area and power restrictions. As a result, new microarchitectural paradigms need to be developed. This work proposes a new organization for x86 processors, based on a traditional superscalar design coupled to a reconfigurable array. The system exploits the fact that few basic blocks are responsible for most of the instructions that execute in the processor, and transforms these basic blocks into configurations for the reconfigurable array. Each configuration encodes the semantics and dependencies for all instructions in the block, so that the ones already mapped can execute bypassing the fetch, decode and dependency checks stages and improving instruction throughput. Our study on the potential of the architecture shows that performance gains of up to 2.5\(\times \) with respect to a traditional superscalar can be achieved.     

A 32-b RISC/DSP microprocessor with reduced complexity

This paper presents a new 32-b reduced instruction set computer/digital signal processor (RISC/DSP) architecture which can be used as a general purpose microprocessor and in parallel as a 16-/32-b fixed-point DSP. This has been achieved by using RISC design principles for the implementation of DSP functionality. A DSP unit operates in parallel to an arithmetic logic unit (ALU)/barrelshifter on the same register set. This architecture provides the fast loop processing, high data throughput, and deterministic program flow absolutely necessary in DSP applications. Besides offering a basis for general purpose and DSP processing, the RISC philosophy offers a higher degree of flexibility for the implementation of DSP algorithms and achieves higher clock frequencies compared to conventional DSP architectures. The integrated DSP unit provides instruction set support for highly specialized DSP algorithms. Subword processing optimized for DSP algorithms has been implemented to provide maximum performance for 16-b data types. While creating a unified base for both application areas, we also minimized transistor count and we reduced complexity by using a short instruction pipeline. A parallelism concept based on a varying number of instruction latency cycles made superscalar instruction execution superfluous     

On Applying Graph Theory to ILP Analysis

The evaluation of computer architectures requires new tools that complement the customary simulations. Graph theory can help to create a new frame of fine grain parallelism analysis. The differences found between the superscalar performance in x86 and non-x86 processors and the peculiar characteristics of the x86 instruction set architecture recommend to carry out a thorough study of the available parallelism at the machine language layer. Starting off from graph theory foundations, new concepts are introduced, from reduced valence to data dependence matrix D, the latter characterizing a code sequence in a mathematical manner. This matrix satisfies a series of properties and restrictions and provides information about the ability of the code to be processed concurrently. The different sources of data dependencies can be composed, facilitating a way to analyze their final influence on the degree of parallelism.     

数字流水Viterbi译码器的VLSI设计

本文介绍了高速数字流水Ｖｉｔｅｒｂｉ译码器的ＶＬＳＩ设计。在符号４值系统的基础上，给出Ｖｉｔｅｒｂｉ算法的新的功能分解公式，并介绍了用于译码器实现的两个重要的快速运算部件ＡＤＤ和ＭＡＸ的原理及其现场可编程（序）门阵列（ＦＰＧＡ）实现。文中详细讨论了译码器的ＶＬＳＩ结构、设计和性能分析。本文给出的Ｖｉｔｅｒｂｉ译码器可塑性强，并具有高度的并行性和很高的数据吞吐率。     

Microarchitectural innovations: boosting microprocessor performancebeyond semiconductor technology scaling

Semiconductor technology scaling provides faster and more plentiful transistors to build microprocessors, and applications continue to drive the demand for more powerful microprocessors. Weaving the "raw" semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture. This paper overviews some of the microarchitectural techniques that empower modem high-performance microprocessors. The techniques are classified into: 1) techniques meant to increase the concurrency in instruction processing, while maintaining the appearance of sequential processing and 2) techniques that exploit program behavior. The first category includes pipelining, superscalar execution, out-of-order execution, register renaming, and techniques to overlap memory-accessing instructions. The second category includes memory hierarchies, branch predictors, trace caches, and memory-dependence predictors. The paper also discusses microarchitectural techniques likely to be used in future microprocessors, including data value speculation and instruction reuse, microarchitectures with multiple sequencers and thread-level speculation, and microarchitectural techniques for tackling the problems of power consumption and reliability     

On‐Chip Multiprocessor with Simultaneous Multithreading

As more transistors are integrated onto bigger die, an on‐chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on‐chip multiprocessor, called Raptor, which is composed of four 2‐way superscalar processor cores and one graphic co‐processor. To obtain performance characteristics of Raptor, a program‐driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on‐chip multiprocessor designs.