具有寄生极点的二阶电流模式滤波器的可调性

积分器寄生极点离主极点不是很远时,会引起全集成滤波器参数的偏差。文中分析了积分器有限直流增益和非主极点的影响,给出了二阶滤波器极点频率和品质因数的微变公式,研究了滤波器的可调控性。在此基础上,提出了增益可调型电流模式连续时间积分器,用这种积分器实现的滤波器能实现fp和Q的双调控。     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

High-frequency CMOS continuous-time filters

Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants. A simple, fully differential integrator, optimized for phase-error cancellation, forms the basic element; a complete filter consists of intercoupled integrators. The center frequency of the filter is locked to an external reference frequency by a phase-locked loop. A prototype sixth-order bandpass filter with a center frequency of 500 kHz dissipates 55 mW and occupies 4 mm/SUP 2/ in a 6-/spl mu/m CMOS technology.     

Automatic Tuning System for Integrator-Based Continuous-Time Filters

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.     

Continuous-time MOSFET-C filters in VLSI

The desirable features of fully integrated, VLSI-compatible continuous-time filters are discussed. A recently proposed integrated continuous-time filter technique is reviewed, in which MOS transistors are used in place of resistors along with the nonlinearity cancellation and on-chip automatic tuning. The filters obtained using this technique are compared to switched-capacitor filters, digital filters, and continuous-time filters using different techniques. Representative experimental results are given, demonstrating the high performance that can be achieved.     

A CMOS transconductance-C filter technique for very highfrequencies

CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3-μm CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described     

非理想因素对基于CCⅡ全集成连续时间滤波器的影响

本文分析了用CCII实现的积分器的误差函数。在此基础上,研究了由双积分器回路构成的基于CCII全集成连续时间带通滤波器;分析了中心频率p,和Qp,与误差函数幅值E和相位E之间的关系;探讨了CCII非理想因素对p,和Qp的影响。所得结论为设计基于CCII的MOSFET连续时间高阶滤波器提供了依据和改进途径。     

A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-timefilter and second-order equalizer optimized for disk-drive read channels

A fast parasitic-insensitive continuous-time filter and equalizer integrated circuit that uses an active integrator is described. Circuit techniques for excess-phase cancellation and for setting the corner-frequency of the filter and equalizer are also described. These techniques result in a filter and equalizer chip with performance independent of process, supply, and temperature without employing phase-lock loops. The 20-MHz sixth-order Bessel filter and second-order equalizer operate from 5 V and generate only 0.24% (-52 dB) of total harmonic distortion when processing 2-V_pp differential output signals. The device is optimized to limit high-frequency noise and to amplitude equalize the data pulses in hard disk read-channel systems. The device supports data rates of up to 36 Mb/s and is built in a 1.5-μm, 4-GHz BiCMOS technology     

Fully-integrated implementation of large time constant G/sub m/-C integrators

A novel technique is proposed to take advantage of system-level properties of applying negative feedback to an operational transconductance amplifier to implement fully integrated large time constant integrators. Based on the proposed idea a first-order lowpass G _m-C filter as an integrator with a cutoff frequency of 20 Hz has been designed, fabricated and tested. Experimental results are in close agreement with theoretical and simulation results     

Integrable Current-Mode Filter Realisation using Dual-Output Current Conveyors for Low-Frequency Operation

The realisation criteria of continuous-time current-mode (CM) active filters for low frequency operation are investigated. New lossless and lossy integrators for low frequency operation using dual-output current conveyors (DO-CCII) are proposed. Basing on these building blocks, a CM universal filter with low natural frequencies suitable for integrated circuit implementation is presented. Using the proposed filter, natural frequencies as low as a few ten hertz can be achieved on an integrated circuit chip without using any external passive components. The proposed circuit simultaneously produces three basic filter responses at its high impedance outputs and it has good passive and active sensitivity performance.     

Low-Voltage High-Frequency Continuous-Time Filters Based on Simple Transconductors and Miller Integrators

An approach to implement low-voltage continuous-time filters using simple transconductance elements and gain-stage Miller integrators is presented. The technique allows direct translation of an RC active structure or a system block diagram into a CMOS circuit that uses differential pairs as transconductors and gain stages as Miller Integrators. A novel and efficient compensation technique to cancell excess phase in Miller integrators is discussed. A new high-frequency compensated CMOS universal filter structure that has no summing nodes in the main feedback loop is discussed and experimentally verified.     

Design tables for two active RC circuits realizing low-pass polyonimic filters

Realization of RC-active filters, as proposed by Sallen and Key, consists of cascade connection of suitable second- and first-order building blocks. The paper presents design tables for two active RC circuits realizing low-pass polyonimic filters. The functions realized are of second to eighth-order low-pass Butterworth, Chebyshev (with 0.1, 0.5, 1, 2 and 3 dB ripple) and Bessel variety. This method uses simple op-amp integrator blocks and can equally be applied to both continuous-time and switch-capacitor filter designs. The advantages of this method are: simple method of designing LP filters from second to eighth order using integrator blocks (e.g. MAX 274 and MAX 275); low sensitivity to component values; low spread in component values; good tuning; can tune parameter f ₁ (cutoff frequency). The disadvantages of this method are: no independent adjustment of the cutoff frequency and the Q-factor; fixed gain of unity.     

用对数域电流模式积分器实现的高频集成滤波器

文本提出了全差动对数域电流模式积分器．该积分器的时间常数受参考偏流控制,其直流增益可达60dB,在高频它具有比较平坦的相频特性。用该积分器设计的二阶滤波器和1dB波纹五阶Chebyshev低通滤波器,计算机仿真显示,“实际”频响特性几乎是理想的．且频率可在很宽的范围内调控．这种滤波器具有很低的THD。     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

Novel active-compensated variable-phase inverting integrator

A novel variable-phase inverting integrator is presented. Compared to some existing circuits, the circuit proposed has better high-frequency behaviour because it does not require the use of identical amplifiers. This integrator can considerably extend the useful frequency range of the two-integrator-loop and multiple-feedback active filters, reducing excess phase shift of the operational amplifiers.     

A novel technique for the on-chip tuning of monolithic filters

Monolithic analog filters, with the exception of switched capacitor filters need on-chip tuning. Existing schemes of PLL and master-slave techniques use phase control for tuning. The proposed method uses amplitude detection, where the reference voltage itself is derived from the input. Much work has recently been done on active RC continuous-time filters in VLSI [4]-[8]. The heart of all such systems is an integrator with a voltage-variable time-constant (VVI). To generate the control for the VVI, these schemes use either a self-tuning filter (follow the master technique) [5] or a phase-locked loop [8], locking on to a stable reference frequency. Unlike these techniques which are essentially phase-control schemes, what is proposed here is a gain-control scheme.     

Topology-independent predistortion for integrator-based filters

This paper proposes a topology-independent predistortion for filters using integrators. This employs integrators having the same structure, the same-value elements and an electrically controllable unity-gain frequency and compensates for the deviation of frequency characteristics due to excess phase shifts of integrators without knowledge of a filter topology. The effectiveness of the proposed method is demonstrated through SPICE simulations.     

A bipolar integrated continuous-time filter with optimized dynamicrange

In the design of integrated continuous-time filters it is often difficult to choose a proper integrator circuit because the relative merits of the different possibilities are little known. A thorough analysis of all the possible circuits is necessary. In this work, the design and an accurate analysis of the noise and distortion properties of one type of integrator, based on a tunable bipolar transconductor, are given. The analysis is used to optimize the dynamic range, and the results are verified by simulation and measurement. A fifth-order low-pass filter design and implementation are presented to illustrate the usefulness of the designed integrator     

Fully differential bilinear integrator for SC filters

A fully differential bilinear SC integrator, which can be used for SC filter realisations, is proposed. It is parasitic-insensitive and particularly useful in SC filters simulating analogue ladder networks. The design of these filters is different from the commonly used ones, and leads to filters with better sensitivity properties than earlier versions. Realisation of a third-order highpass filter, bilinearly transformed from the continuous-time to the discrete-time domain, is shown as an example.     

Using fractional delay to control the magnitudes and phases of integrators and differentiators

The use of fractional delay to control the magnitudes and phases of integrators and differentiators has been addressed. Integrators and differentiators are the basic building blocks of many systems. Often applications in controls, wave-shaping, oscillators and communications require a constant 90deg phase for differentiators and -90deg phase for integrators. When the design neglects the phase, a phase equaliser is often needed to compensate for the phase error or a phase lock loop should be added. Applications to the first-order, Al-Alaoui integrator and differentiator are presented. A fractional delay is added to the integrator leading to an almost constant phase response of -90deg. Doubling the sampling rate improves the magnitude response. Combining the two actions improves both the magnitude and phase responses. The same approach is applied to the differentiator, with a fractional sample advance leading to an almost constant phase response of 90deg. The advance is, in fact, realised as the ratio of two delays. Filters approximating the fractional delay, the finite impulse response (FIR) Lagrange interpolator filters and the Thiran allpass infinite impulse response (IIR) filters are employed. Additionally, a new hybrid filter, a combination of the FIR Lagrange interpolator filter and the Thiran allpass IIR filter, is proposed. Methods to reduce the approximation error are discussed.