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1.
本文介绍了一款具有较高输出功率和宽调谐频率范围的基波压控振荡器单片集成电路。其制作工艺为fT =170GHz,fmax =250GHz的0.8um InP DHBT工艺。电路核心部分采用了平衡式考毕兹振荡器拓扑,并在后面添加了一级缓冲放大器来抑制负载牵引效应,并提升了输出功率。DHBT的反偏CB结作为变容二极管来实现频率调谐。芯片测量结果表明,VCO的频率调谐范围为81- 97.3GHz,相对带宽为18.3 %。在调谐频率范围内最大输出功率为10.5 dBm,输出功率起伏在3.5 dB以内。在该VCO的最大调谐频率97.3 GHz处相位噪声为-88 dBc/Hz @1MHz。在目前所报道的InP HBT基VCO MMIC中,本文在如此宽的频率调谐范围内实现了最高的输出功率。  相似文献   

2.
蔡运城  曹军  赵君鹏  吴凯翔  高海军 《微电子学》2020,50(1):90-94, 100
提出了一种2 μm GaAs HBT工艺的低相噪宽带压控振荡器(VCO)。与CMOS工艺相比,采用HBT工艺设计的VCO噪声性能更好,具有较大的电流放大倍数和跨导。该VCO采用差分 Colpitts 结构,并对无源器件进行结构优化,在4.1 GHz处,片上螺旋电感的品质因数超过21,实现了较低的相位噪声。通过二极管组成变容阵列,实现了较宽的调谐范围。流片测试结果表明,VCO 调谐范围为3.370~4.147 GHz,最大输出功率为-16.13 dBm,直流功耗为43 mW。在振荡频率为 4.1 GHz 时,相位噪声为-125.2 dBc/Hz@1 MHz。该VCO在相对较宽的调谐范围内实现了较低的相位噪声。  相似文献   

3.
本文叙述了采用单变容管调谐的4~8GHz共漏反沟道GaAs FET VCO的设计和研究结果。振荡器的直接输出功率大于16.5dBm,功率平坦度为±2dBm,线性度优于3:1(电调灵敏度之比)。并给出了振荡器其他性能。  相似文献   

4.
设计了一种全集成交叉耦合变压器反馈的LC压控振荡器(LC-VCO),该VCO在电源电压低于阈值电压的情况下实现了超低功率消耗和低相位噪声.该超低功耗的VCO采用SMIC 0.18μm数模混合RF 1P6M CMOS工艺进行了流片验证.测试结果表明:电路在0.4V电源供电和工作频率为2.433GHz时,相位噪声为-125.3dBc/Hz(频偏1MHz),核心直流功耗仅为720μW.芯片的工作频率为2.28~2.48GHz,调谐范围为200MHz(8.7%),电路的优值为-193.7dB,信号的输出功率约为1dBm.该VCO完全可以满足IEEE 802.11b接收机的应用要求.  相似文献   

5.
基于65nmCMOS工艺实现了60GHz推—推压控振荡器(VCO)设计。采用互补交叉耦合去尾电流源结构以降低相位噪声。压控振荡器输出包含两级缓冲放大器,第二级缓冲放大器偏置在截止区附近以增大二次谐波的输出功率。在1.2/0.8V电源电压下,压控振荡器核心和缓冲放大器分别消耗2.43mW和2.95mW。在偏离中心频率1MHz处相位噪声为-90.7dBc/Hz。输出功率为-2.92dBm。特别的,压控振荡器的调谐范围达到9.2GHz(15.3%),与调谐范围相关的性能指标FOMT为-182.7dBc/Hz。该压控振荡器可应用于57GHz~64GHz开放频段超高速短距离无线通信。  相似文献   

6.
通过提高MIM电容的调整范围,实现了一个覆盖3.2~6.1 GHz的CMOS LC VCO.该VCO使用0.18μm射频CMOS工艺制作,芯片面积约为1260μm×670μm.当输出5.5GHz时,VCO内核消耗功率为17.5mW;在100kHz频偏处的相位噪声是~101.67dBc/Hz.  相似文献   

7.
频率覆盖3.2~6.1 GHz的CMOS LC VCO   总被引:2,自引:0,他引:2  
通过提高MIM电容的调整范围,实现了一个覆盖3.2~6.1 GHz的CMOS LC VCO.该VCO使用0.18μm射频CMOS工艺制作,芯片面积约为1260μm×670μm.当输出5.5GHz时,VCO内核消耗功率为17.5mW;在100kHz频偏处的相位噪声是~101.67dBc/Hz.  相似文献   

8.
介绍了一种采用新颖谐振器的低相位噪声窄带压控振荡器(VCO)的设计方法。该谐振器采用源与负载横向交叉耦合结构,形成一个传输零点,提高了谐振器的Q值。该谐振器通过弱耦合与变容二极管连接,从而实现电压控制滤波器通带中心频率调谐。利用该谐振器设计了一个窄带VCO,并在先进设计系统(ADS)软件里仿真验证。该VCO中心频率6.15 GHz,在调谐电压从0到15 V的范围内调谐带宽60 MHz,相位噪声在整个调谐范围内优于-132 dBc/Hz@1MHz,输出功率为8.4 dBm,功率平坦度±0.1 dBm。  相似文献   

9.
设计并流片制作了基于GaAs PHEMT工艺的Ka波段微波单片集成压控振荡器(MMIC VCO).该VCO具有紧凑、宽电调谐带宽及高输出功率的特点.提出了缩小芯片面积及增大调谐带宽的方法,同时还给出了设计MMIC VCO的基本步骤.该方法设计并流片制做的MMIC VCO的测量结果为:振荡频率为36±1.2GHz,输出功率为10士1dBm,芯片面积为1.3mm×1.0mm.  相似文献   

10.
设计了一款宽带CMOSLCVCO,在分析VCO相位噪声来源的基础上,对VCO进行了结构优化和噪声滤除,并采用了开关电容阵列以增加带宽。电路采用0.18μmCMOS射频工艺进行流片验证,芯片面积为0.4mm×1mm。测试结果显示:芯片的工作频率为3.34~4.17GHz,中心频率为4.02GHz时输出功率是-9.11dBm,相位噪声为-120dBc/Hz@1MHz,在1.8V工作电压下的功耗为10mW。  相似文献   

11.
This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2.  相似文献   

12.
基于TSMC 180 nm CMOS工艺,提出了一种振荡频率为2~3 GHz的宽频率范围、低相位噪声的单子带压控振荡器(VCO)。采用双平衡吉尔伯特混频结构,将单子带5~6 GHz压控振荡器与固定频率3 GHz压控振荡器进行下混频,可得到振荡频率为2~3 GHz的单子带压控振荡器,实现相对带宽从18.18%到40%的展宽。其中5~6 GHz单子带压控振荡器采用互补交叉耦合结构,更易达到起振条件,采用两组可变电容的并联形式以提高调谐曲线的线性度,拓宽压控振荡器的输出频率调谐范围。通过芯片测试验证,在1.8 V电源电压下,调谐电压变化范围为0.6~2.8 V时,实际输出频率范围为1.85~3 GHz,最大调谐灵敏度为1000 MHz/V,2 GHz频点处相位噪声为-123.2 dBc/Hz@1 MHz,芯片尺寸为1.2 mm×0.7 mm。  相似文献   

13.
In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.  相似文献   

14.
A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.  相似文献   

15.
The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.  相似文献   

16.
A fully integrated K-band balanced voltage controlled oscillator (VCO) is presented. The VCO is realized using a commercially available InGaP/GaAs heterojunction bipolar transistor (HBT) technology with an f/sub T/ of 60 GHz and an f/sub MAX/ of 110 GHz. To generate negative resistance at mm-wave frequencies, common base inductive feedback topology is used. The VCO provides an oscillation frequency from 21.90 GHz to 22.33 GHz. The frequency tuning range is about 430 MHz. The peak output power is -0.3 dBm. The phase noise is -108.2 dBc/Hz at 1 MHz offset at an operating frequency of 22.33 GHz. The chip area is 0.84/spl times/1.00 mm/sup 2/.  相似文献   

17.
A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression, over 45 dB, for the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB.  相似文献   

18.
A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.  相似文献   

19.
A balanced Colpitts voltage-controlled oscillator (VCO) is designed and fabricated in a commercially available 0.25-/spl mu/m SiGe BiCMOS process. It has the characteristics of the push-push VCO, i.e., the VCO has simultaneously a differential output at a fundamental frequency of 21.5 GHz and a single-ended output at the second harmonic frequency of 43 GHz. A differential tuning technique is applied to reduce the phase noise. The measured phase noise at 1-MHz offset is -113 dBc/Hz at 21.5 GHz and -107 dBc/Hz at 43 GHz. The corresponding output power is about -6 and -17 dBm, respectively, with a 5% tuning range and a 130-mW dc power consumption.  相似文献   

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