适用于无源射频标签的低功耗单栅非挥发性存储器

针对低成本、低功耗无源射频电子标签,采用SMIC 0.18μm标准CMOS工艺设计实现了单栅、576bit的非挥发性存储器.存储器单元基于双向Fowler-Nordheim隧穿效应原理并采用普通的pMOS晶体管实现;编程/擦写时间为10ms/16bit.芯片实现块编程和擦写功能,通过提出一种新型的敏感放大器而实现了读功耗的优化.在电源电压为1.2V,数据率为640kHz时,读操作平均消耗电流约为0.8μA.     

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

一种适用于射频电子标签的超低功耗嵌入式EEPROM

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

适用于无源RFID标签芯片的SPNVM优化设计

稳定的非挥发性存储器(Non-volatile memory,NVM)是射频识别标签系统中的重要组成部分,作为系统的信息承载体,用于存储用户或产品的基本信息。NVM的性能和造价是约束其发展的主要因素,为了改善非挥发性存储器的性能和降低其成本,文中基于传统的非挥发性存储器EEPROM,采用UMC 0.18μm标准CMOS工艺,优化设计了一个存储容量为256位高性能低成本的单栅非挥发性存储器,从工作电压、效率、速度和功耗的角度,对存储单元进行了隔离保护处理,改进了电荷泵的升压模块和稳压模块,采用电压检测型灵敏放大器。电源电压1.8V,编程电流为42μA,读电流为2μA,编程时间为5ms/bit,读速率为2Mb/s。     

Ge/Si复合纳米结构电荷存储特性的模拟研究

这一研究工作模拟计算了 Ge/ Si复合纳米结构 MOSFET存储器的擦写和存储时间特性。结果表明 ,Ge/ Si复合纳米结构存储器在低压下即可实现 μs和 ns量级编程。与 Si纳米结构存储器相比 ,由于 Ge/ Si复合势阱的作用 ,器件的电荷保留时间提高了 3～ 5个量级 ,有效地解决了快速擦写编程与长久存储之间的矛盾 ,使器件的性能得到明显改善。     

RFID中EEPROM时序及控制电路设计

RFID系统对电子标签中的存储器有着不同于传统存储器的要求。根据这一特点进一步简化了EEPROM的时序控制,提出了一种适用于RFID系统中EEPROM电路的时序,并在此基础上设计了用于电子标签完成读卡器要执行的命令和对处理数据存储的控制电路,使操作变得更加便捷。该电路设计基于0.35μmCMOS工艺,电源电压为3.3V,仿真结果显示,3.3V电源供电时,擦写编程电流为45μA,读数据工作电流为3μA,读数据周期为300ns,具有低功耗、高速度的特性。     

门极驱动光耦改善电机逆变器精度与效率

与FLASH和E2PROM这些非易失性存储器相比,铁电存储器(FRAM)具有RAM级别的写入速度,能实现无限次数的擦写(FLASH和E2PROM在经过一定擦写次数后可靠性明显下降),还可以采用低电压进行写入而无需在系统中添加电压泵.     

4兆位FRAM采用130nm工艺生产

与FLASH和E2PROM这些非易失性存储器相比,铁电存储器(FRAM)具有RAM级别的写入速度,能实现无限次数的擦写(FLASH和E2PROM在经过一定擦写次数后可靠性明显下降),还可以采用低电压进行写入而无需在系统中添加电压泵.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.     

一个用于12位40-MS/s低功耗流水线ADC的MDAC电路设计

文中设计了一个用于12位40MHz采样率低功耗流水线ADC的MDAC电路.通过对运放的分时复用,使得一个电路模块实现了两级MDAC功能,达到降低整个ADC功耗的目的.通过对MDAC结构的改进,使得该模块可以达到12bit精度的要求.通过优化辅助运放的带宽,使得高增益运放能够快速稳定.本设计在TSMC0.35μmmixsignal3.3V工艺下实现,在40MHz采样频率下,以奈奎斯特采样频率满幅(Vpp=2V)信号输入,其SINAD为73dB,ENOB为11.90bit,SFDR为89dB.整个电路消耗的动态功耗为9mW.     

小面积低功耗掩膜ROMASIC设计

本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构,整个芯片的面积为0.082mm².在5伏电源下,功率延迟积为0.036PJ/bit,最大工作电流为1.2mA,最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度,ROM的访问时间为36ns.     

Design of replica bit line control circuit to optimize power for SRAM

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.     

Design techniques of low-power embedded EEPROM for passive RFID tag

This paper presents an optimized embedded EEPROM design approach which has reduced the power significantly in a short-range passive RFID tag. The proposed array control circuit employs an improved structure to minimize the leakage of memory bit cells. With the proposed array circuit design, the passive RFID tag can operate drawing a low quiescent current. The RFID tag with the proposed EEPROM was fabricated in a standard 0.35-μm four-metal two-poly CMOS process. Measurement results show that the erasing/writing current is 45 μA, and reading current consumption is 3 μA with a supply voltage of 3.3 V. The data read time is 300 ns/bit.     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

一种低功耗扩展计数型模数变换器设计

扩展计数型模数变换器(ADC)结合了ΣΔ调制器高精度和Nyquist速率ADC速度相对较快的优点,因而获得了广泛的重视。设计了一种13bit的扩展计数型ADC,设计中采用了1.5bit量化技术和硬件复用技术,其中,1.5bit量化技术降低了系统对比较器精度的要求,因而可使用动态比较器来降低系统的功耗。硬件复用技术利用了扩展计数型ADC两步变换分时操作的特点,采用同一套模拟器件实现了两个变换过程,既降低了系统功耗,又减小了核心电路的面积。上述设计采用0.18μm CMOS混合信号工艺流片验证,芯片核心部分的面积只有0.06mm2。测试结果表明该ADC的有效位数(ENOB)为10.6bit,在19.5ks/s的转换频率下功耗只有115μW。     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩.利用这些技术,ROM尺寸压缩了98%.采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2.在3.3V电源下,该芯片的功耗为167mW,无杂散动态范围(SFDR)为61dB.     

单片GaAs 3bit相位DAC的设计与实现

详细论述了用于数字射频存储器系统的单片超高速GaAs 3bit相位DAC的设计、制造及测试.在南京电子器件研究所标准75mm GaAs工艺线采用0.5μm全离子注入MESFET工艺完成流片.芯片输入输出阻抗实现在片50Ω匹配.测试结果表明,其工作带宽大于1.5GHz,相位精度小于4%,电路的码流翻转速率大于12Gbps.     

A new low-power GaAs two-single-port memory cell

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm² using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V