无铅再流焊接PBGA空洞缺陷研究

随着密间距BGA、CSP器件的大量应用,该类器件在焊接中的空洞问题也越来越受到人们的重视.而无铅制程的导入使得这一问题表现得更加突出.基于对多个实际案例的解剖、分析、试验的统计数据基础上,对产品生产过程中所发生的PBGA、CSP的空洞现象进行了分类归纳.并一一研究了其形成机理、影响因素及抑制对策.     

HDI多层印制电路板无铅再流焊爆板问题研究

HDI多层印制电路板在无铅再流焊接中的爆板现象是严重威胁产品质量、导致生产线不能正常运转甚至停线的较严重的质量事件.重点分析了无铅再流焊接过程中最常见的爆板现象,讨论了爆板发生的机理,并在此基础上探讨了抑制爆板的技术措施.     

现代电子装备高密度组装技术

本文介绍了QFP、BGA、CSP芯片的类型、封装结构、焊点结构及其可靠性，论述了其在高密度组装和再流焊接中的技术挑战，分析了再流焊接中的共面性和问题。同时简要介绍了BGA、CSP组装件的检测技术。     

解决BGACSP球窝缺陷的实际案例分析

随着无铅应用要求的普及，特别是BGA和CSP元件转变成无铅之后，BGA、CSP的球窝缺陷（Head—In-Pillow，HIP）成为电子制造业中非常常见的缺陷之一。球窝缺陷的表现形式为锡球好像是与整个锡膏连接在一起，但实际上它只是放在没有形成相互融合的窝坑里或突堆上，即便能通过所有功能测试，其可靠性失效的几率也彳艮高。因此该缺陷的危害很大。有很多潜在的因素可能会导致球窝缺陷：例如元件封装的变形、不同的BOA焊球合金成分、BOA锡球的氧化、回流焊工艺的类型、回流曲线、锡膏的化学成分等。因此，对于解决球窝缺陷存在有很多不同的观点。本文介绍了一个消除球窝缺陷的实际案例。通过对球窝缺陷形成的机理进行分析，并通过一系列的失效分析，我们采用了回流曲线优化和抗球窝锡膏的措施成功地解决了球窝缺陷。本文同时也介绍了一种非常有效的非破坏性检测方法来快速验证球窝缺陷的解决情况。     

再流焊常见缺陷的成因及解决办法

对采用表面贴装技术生产的印制电路组件在再流焊接中出现的桥接、焊料球、立碑等焊接缺陷进行了分析，并提出了一些有效的解决办法。     

再流焊常见缺陷的成因及解决办法

对采用表面贴装技术生产的印制电路组件在再流焊接中出现的桥接、焊料球，立碑等焊接缺陷进行了分析，并提出了一些有效的解决办法。     

BGA无铅焊点零空洞缺陷控制研究

在无铅BGA封装工艺过程中,通过不同组分的BGA焊球合金与焊膏合金组合焊接、焊膏助焊剂活性剂不同配比及其不同再流焊接条件等实验,对焊料合金和助焊剂配比、再流焊接峰值温度、再流保温时间等参数变化,以降低BGA焊点空洞缺陷进行了研究。结果表明选用相同或相似的BGA焊球和焊膏合金组合焊接、选用活性强的焊膏、选择焊接保温时间较长均有助于降低BGA焊点空洞缺陷产生的几率和空洞面积,BGA焊点最佳再流焊接峰值温度为240℃,当峰值温度设置为250℃时,BGA焊点产生空洞缺陷几率会比240℃高出25%～30%。     

表面组装焊接技术——激光再流焊

激光再流焊接技术主要适用于军事和航空航天电子设备中的电路组件的焊接。这些电路组件采用了金属芯和热管式PCB,贴装有QFP和PLCC等多引脚表面组装器件。由于这些器件比其他SMC／SMD的热容量大,采用VPS需增加加热时间,这将导致PCB和表面组装器件出现可靠性问题。波峰焊接和红外再流焊接技术也不适用于这种情形下的焊接,但激光再流焊接技术可快速在焊接部位局部加热而使焊料再流,避免了用上述焊接技术的缺陷。同时,由细间距器件组装的SMC／SMD在成组的再流焊接工艺中常出现大量桥连和开口。特别是随着引脚数目的增加和引脚间距的缩小,引脚的非共面性使这些焊接缺陷显著增加。     

0.5 mm间距CSP焊接工艺研究

随着对各种电子产品，尤其是消费类电子产品的便携性和多功能的追求，CSP等新型封装器件(封装尺寸约为芯片本身尺寸的1．2倍)便应用到这些产品的设计中去。CSP器件的引脚间距有0．8mm、0．75mm、0．65mm、0．5mm等。为了便于以后产品设计和生产的需要，就CSP器件在PWB设计和焊接两方面进行研究，侧重于焊接方面。     

印制线路板翘曲对高温下球栅阵列的影响

为确定在再流焊接过程中印制线路板翘曲的程度及其印制线路板翘曲对焊接到板子上的球栅陈列的影响而进行了一项研究。目的之一是确定印制线路翘曲与球栅陈列的开路之间是否有关系。     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

BGA组装技术及其质量控制

BGA器件已越来越广泛地应用到电子产品中,并且随着μBGA和CSP的出现,组装难度越来越大,工艺要求也越来越高。主要分析了影响BGA组装质量的各个环节因素,从工艺控制、组装操作、管理和检测判定等四个方面详细阐述了控制质量关键点及实施要求。     

高密度封装技术的发展

本文简要介绍了BGA与CSP的概念、发展现状、应用情况及发展趋势等。BGA／CSP是现代组装技术的两个新概念，它们的出现促进SMT(表面贴装技术)与SMD(表面贴装元器件)的发展和革新，并将成为高密度、高性能、多功能及高I／O数封装的最佳选择。     

倒装晶片(Flip Chip)装配工艺及其对表面贴装设备的要求

元件的小型化高密度封装形式越来越多,如多模块封装(MCM),系统封装(SiP),倒装晶片(FC)等应用得越来越多。这些技术的出现更加模糊了一级封装与二级装配之间的界线,勿庸置否,随着小型化高密度封装的出现,对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。由于倒装晶片比BGA或CSP具有更小的外形尺寸,更小的球径和球间距,它对植球工艺,基板技术,材料的兼容性,制造工艺以及检查设备和方法提出了前所未有的挑战。     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

倒装晶片装配工艺及其对表面贴装设备的要求

随着市场对于电子产品特别是消费型电子产品持续要求越来越高,要求其短小轻薄、功能高度集成、价格更加便宜、储空间更大,元件的小型化高密度封装形式越来越多,如多模块封装（MCM）、系统封装（SiP）、倒装晶片（FC）等应用得越来越多。这些技术的出现更加模糊了一级封装与二级装配之间的界线,勿庸置否,随着小型化高密度封装的出现,对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。由于倒装晶片比BGA或CSP具有更小的外形尺寸,更小的球径和球间距,它对植球工艺、基板技术、材料的兼容性、制造工艺以及检查设备和方法提出了前所未有的挑战。     

0.5mm间距CSP/BGA器件无铅焊接工艺技术研究

芯片级封装器件因其小尺寸、低阻抗、低噪声等优点广泛应用于电子信息系统中.从器件封装、印制板焊盘设计、焊膏印刷、贴装以及回流焊接等方面探讨了0.5 mm间距CSP/BGA器件无铅焊接工艺技术.     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

Optimal design for a ball grid array wire bonding process using aneuro-genetic approach

This study presents an integrated method in which neural networks, genetic algorithms, and exponential desirability functions are used to optimize the ball grid array (BGA) wire bonding process. As widely anticipated, the BGA package will become the fastest-growing semiconductor package and push integrated circuit (IC) packaging to higher level of compactness and density. However, wire bonding in BGA is difficult owing to its high input/output (I/O) count, fine pitch wire bonds, and long wire lengths. This study addresses two fundamental issues in the semiconductor assembly facility on its quest toward a defect-free manufacturing environment. First, the problem of exploring the nonlinear multivariate relationship between parameters and responses and second, obtaining the optimum operation parameters with respect to each response in which the process should operate. The implementation for the proposed method was carried out in an IC assembly factory in Taiwan; results in this study demonstrate the practicability of the proposed approach