一种接收前端三级低噪声放大器的设计

针对单片雷达接收机中对低噪声放大器（LNA）的要求,采用CMOS0．18m工艺设计了三级级联的镜像抑制低噪声放大器。通过在低噪声放大器中接入陷波滤波器,实现对镜像信号的衰减,从而减小了后端混频器电路的设计难度。在ADS中对放大器进行仿真,结果表明：在最大供电电压为5V、信号频段为3．0～3．2GHz时,中频输出225MHz,功率增益31dB,噪声系数（NF）0．5dB,输入输出1—dB点的功率分别为-19．5和11．5dBm,对镜像信号的抑制度达22dB。     

一种集成镜像抑制的低噪声放大器设计

为解决超外差接收机中镜像干扰的问题,采用了一种有源陷波滤波器(active notch-filter)来实现镜像抑制功能。并在此基础上设计了用于数字音频广播(Digital Audio Broadcast,DAB)系统的低噪声放大器。该LNA电路工作在L-band1.472GHz,,经过第一次变频到165MHz,其镜像频率为1.142GHz,有源陷波滤波器可提供超过55dB的镜像抑制度。整个LNA电路采用1.8V电源,消耗5mA电流,S11和S22分别为-22dB和-16dB,功率增益为21dB。噪声指数为1.45dB,输入P1db点为-25dBm。     

CMOS低功耗窄带低噪声放大器优化设计

阐述了一个采用Chartered 0.35 μm CMOS工艺实现的应用于315 MHz幅度键控接收芯片的低功耗窄带低噪声放大器.该电路主要采用限定功耗下同时优化噪声性能和输入匹配的技术进行设计,并且采取了其他一些措施来进一步改善电路的性能.采用一个并-串谐振网络,提供镜像抑制.实验测试表明,该低噪声放大器的噪声系数为1.47 dB,功率增益为19.97 dB,输入三阶截断点为-15.53 dBm,镜像抑制为42.4 dB,功耗为1.4 mW.     

双频段接收机中的BiFET低噪声放大器

设计了一种采用BiFET结构的低噪声放大器（LNA），这种结构通过BiCMOS工艺使低噪声放大电路集合了双极型晶体管的低噪声特性和CMOS晶体管的高线性度。应用优化的BiFET Cascode共源共栅结构能够明显地提高低噪声放大器的性能，并且能应用于两个不同频率。本文设计的低噪声放大器在低偏置电流（1．7mA）和低功耗（5．7mW）的情况下能取得1．69dB的噪声系数、15．96dB的电压增益、一8．5dBm的IIP3和-67dB的反向隔离。设计的BiFET低噪声放大器是采用了AMS0．8μm的BiCMOS混合信号工艺,经过优化可以用于工业、室内的远程无线控制系统包括无线门禁系统。     

X波段微波低噪声混合集成接收前端

介绍了低噪声GaAsFET用作单脉冲跟踪雷达前端放大时的持点、系统构成以及低噪声放大器和镜像抑制混频器的设计方法和制作。测试结果性能满意，在近1GHZ频率范围内系统总噪声系数小于2．5dB，放大器增益大于20dB，混频器镜像抑制度大于20dB，三路放大器之间幅度不平衡小于0．8dB，相位不平衡小于7°。该混合集成微波前端已成功地用于某型火控雷达，对海面上低空小目标进行跟踪。     

C波段低噪声放大器的设计

介绍了C波段低噪声放大器的设计和研制过程,并给出了研制结果.它采用平衡式电路结构来达到宽带、低噪声的性能.该放大器在5～6GHz的性能指标为:小信号功率增益GP≥30dB,增益波动△GP≤0.8dB,输出P-1≥10dBm,噪声系数NF≤1.0dB,输入驻波比≤1.2:1,输出驻波比≤1.2:1.     

基于薄膜工艺的x波段下变频器设计

本文介绍了一个基于薄膜电路工艺设计、加工的X波段下变频器.首先对整体方案进行分析论证,然后运用安捷伦公司的ADS仿真设计软件,对射频及中频滤波器、朗格电桥、低噪声放大器和混频器等电路单元及变频器系统进行了仿真设计.最后经过加工测试验证,该变频器性能指标良好.其工作频率为9.35GHz - 9.85GHz,变频增益≥26dB,噪声系数≤2dB,P01dB压缩点功率≥10dBm,输入、输出驻波≤1.3,镜像抑制比≥50dB;本振输入为0±1dBm.整个电路腔体结构尺寸为70mm×20mm×10mm.     

一种新型低噪声掺Er光纤放大器的研究

提出了一种新型的低噪声掺Er光纤放大器(EDFA)。将光波长交错器的输入端口与普通EDFA的输出端相连接,用于降低噪声,信号光由光波长交错器的偶信道端口输出。利用光波长交错器的梳状反射特性,抑制EDFA的放大自发辐射(ASE),改善EDFA的噪声特性,使其具有低噪声的特点。采用4m长的掺Er光纤(EDF)作为增益介质,小信号功率为-26dBm时,在1530～1560nm带宽范围内,测得低噪声EDFA的噪声系数低于3.83dB,仅比噪声系数的量子极限3dB大0.83dB。     

毫米波GaAs单片限幅低噪声放大器

设计了一款毫米波GaAs单片限幅低噪声放大器。限幅器采用两级反向并联二极管结构,通过优化限幅器匹配电路,增大了限幅器的耐功率,降低了限幅电路的插损。低噪声放大器为四级级联设计,输入端采用最小噪声匹配,偏置电路增加RC串联谐振电路,减小了噪声,提高了电路稳定性。测试结果表明,该毫米波GaAs单片限幅低噪声放大器在33～37 GHz频带内,增益达到22 dB,增益平坦为±1 dB,输入驻波小于2,输出驻波小于1.5,噪声小于3.0 dB,输出1 dB增益压缩点(P_(1dB))大于5 dBm,可以承受15 W的脉冲输入功率。     

基于GP2015的GPS射频前端电路ADS优化设计

根据“超外差”结构设计了一种以GP2015为核心的GPS射频前端接收电路,混频级数设计为3级,混频输出的中频信号进行多次优化滤波。首先利用ADS2008系统建模和行为级功能仿真验证系统可行性,其次选择合适的低噪声放大器对射频信号进行放大,提高了接收机的接收灵敏度,最后对PCB板的线宽进行阻抗匹配、电路制作及电路滤波优化。测试结果表明,该电路成功地实现了射频信号的下变频及接收,输出信号功率达到-3.3 dBm,镜像抑制能力达到37 dB。     

Design of low-voltage cmos low-noise amplifier with image-rejection function

A new design is presented that combines a low-noise amplifier (LNA) with an on-chip filter instead of external filter to eliminate image signal based on TSMC 0.18 mum CMOS technology. The fully integrated 5.9 GHz LNA exhibits 15.2 dB gain, 3.2 dB noise figure, better than -15 dB input and output return loss, and -27 dB image rejection. The circuit operates at a supply voltage of 1 V and consumes only 6.1 mW power.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

A Sub-2 dB NF Dual-Band CMOS LNA for CDMA/WCDMA Applications

This letter presents the design and experimental results of a 1.8/2.14 GHz dual-band CMOS low-noise amplifier (LNA), which is usable for code division multiple access and wideband code division multiple access applications. To achieve the narrow-band gain and impedance matching at both bands, an extra capacitor in parallel with the C_gs of the main transistor and a harmonic tuned load are switched. Except for the output blocking capacitor and series inductor, all components are integrated on a single-chip. The LNA is designed using a 0.13mum- CMOS process and employs a supply voltage of 1.5 V and dissipates a dc power of 7.5 mW. The measured performances are gains of 14.54 dB and 16.6 dB, and noise figures of 1.75 dB and 1.97 dB at the two frequency bands, respectively. The linearity parameters of and P1dB_in are -16dBm and -5.8 dBm at the 1.8 GHz, -14.8 dBm and -5.3 dBm at the 2.14 GHz, respectively.     

A C-band high-dynamic range GaN HEMT low-noise amplifier

A C-band low-noise amplifier (LNA) is designed and fabricated using GAN HEMT power devices. The one-stage amplifier has a measured noise figure of 1.6 dB at 6 GHz, with an associated gain of 10.9 dB and IIP3 of 13 dBm. it also exhibits broadband operation from 4-8 GHz with noise figure less than 1.9 dB. The circuit can endure up to 31 dBm power from the input port. Compared to circuits based on other material and technology, the circuit shows comparable noise figure with improved dynamic range and survivability.     

0.6V CMOS低噪声放大器的设计与优化*

采用SMIC 0.18 μm CMOS工艺设计了一个低电压低功耗的低噪声放大器(Locked Nucleic Acid,LNA).分析了在低电压条件下LNA的线性度提高及噪声优化技术.使用Cadence SpectreRF仿真表明,在2.4 GHz的工作频率下,功率增益为19.65 dB,输入回波损耗S11为-12.18 dB,噪声系数NF为1.2 dB,1 dB压缩点为-17.99 dBm,在0.6V的供电电压下,电路的静态功耗为2.7 mW,表明所设计的LNA在低电压低功耗的条件下具有良好的综合性能.     

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 Ω Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-/spl mu/m CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.