高集成Ku 波段雷达信号传输网络研究与设计*

采用复杂信号传输一体化集成设计技术,设计了一种高集成、小型化、高可靠雷达信号传输网络,其具备射频信号(14G鄄18G)功率分配合成、波控控制信号分配传输、电源分配等功能。同时还通过射频、数字信号协同仿真技术对网络进行EMI(电磁干扰)及SI(信号完整性)分析和优化,显著改善了在复杂电磁环境下,Ku 波段宽带射频信号传输网络易谐振,控制信号反射和串扰明显的现象,提升了信号传输质量,实测结果验证了仿真的精确有效。文中所阐述的设计方法是对传统雷达阵面技术的革新,符合现代雷达阵面高集成、小型化、电磁环境复杂、可靠性要求高的发展趋势。     

FPGA片内PLL电磁抗扰度的热应力效应测试分析

针对集成电路(IC)在复杂物理环境中的电磁抗扰度漂移问题,研究了环境热应力对基于供电网络传导耦合的现场可编程逻辑门阵列(FPGA)内嵌锁相环(PLL)电路电磁抗扰度的影响。分析典型FPGA片内PLL的功能原理及电磁干扰机理;将环境热应力干扰因素引入PLL电磁抗扰度测试研究中,设计基于电磁干扰直接功率注入(DPI)与热应力耦合的抗扰度测试平台;测试分析了在20～110℃热应力范围内,电磁干扰分别通过1.2 V、2.5 V和IC地电源网络注入片内PLL时,其电磁抗扰度特性变化。结果表明,当片内PLL功能单元受到不同注入路径的电磁干扰时,其在不同频段的电磁抗扰度变化趋势基本一致;考虑热应力因素影响时,片内PLL的电磁抗扰度特性会发生明显漂移,且当锁相环的2.5 V工作电压受到电磁-热复合应力干扰时,PLL的电磁抗扰度最弱,热应力干扰因素加剧了其抗扰度的漂移。     

EMC认证的检验项目

家用电器产品EMC认证进行的EMC检验项目包含电磁发射(EMI)和电磁抗扰度(EMS)两个方面。电磁发射(EMI)的检验项目有:①.连续干扰电压(150kHz～30MHz);②.断续干扰电压(150kHz、500kHz、1.4MHz和30MHz);③.干     

在甚高频范围内同轴电缆抗电磁场干扰的测试

讨论了一种屏蔽电缆抗扰性测量的新方法,这种方法是意大利都灵的国立电工技术研究所(IEN)发明的。按照此方法,被测的抗扰性是电磁场在一根基准裸线上的感应电压与在同样场强下在电缆编织内表面上的感应电压之比。用一只同轴截止滤波器沿着被测电缆及裸导线滑动,调谐到工作频率,以改善此方法的灵敏度。此方法可在室内采用,和按照国际电工委员会的(IEC)标准方法测量出的表面转移阻抗相比较,其结果良好。     

介质型EBG结构对同步开关噪声抑制的有限元分析

研究了介质型电磁带隙结构对高速电路中电源/ 地平面间同步开关噪声的抑制作用。该介质型电磁带隙结构在抑制同步开关噪声的同时未破坏高速信号的电流返回路径,使高速信号的信号完整性得以保持。利用电磁场有限元方法将电源/地平面间同步开关噪声抑制的三维问题转化成二维问题进行处理,提高了计算效率。分析了介质型电磁带隙结构的介电常数对噪声抑制带宽的影响,利用了三维全波电磁场仿真软件HFSS对二维数值结 果进行仿真验证,仿真结果与数值计算结果基本吻合,验证了二维数值算法的正确性。     

常用电磁干扰电平的换算

常用电磁干扰电平的换算张志中近年来，频谱分析仪在电磁干扰测量中使用已很广泛，而频率合成信号发生器在电磁抗扰测量中使用也很广泛。频谱分析仪常用功率电平来显示被测信号的强度，也有用电压电平来显示被测信号大小的。频率合成信号发生器常用功率电平来显示所产生的...     

射频场感应的传导骚扰抗扰度能力验证测量

该文主要介绍射频场感应的传导骚扰抗扰度测量设备系统的评估,及能力验证测量。     

书讯

该书主要介绍了电磁兼容(EMC)的基本概念和原理,各种电磁干扰产生的机理和模型,减少干扰及提高抗扰度的方法,电磁场的生物效应与人体暴露限值,系统的EMC和天线耦合的分析,电磁干扰(EMI)的预估技术和计算机电磁建模的方法,以及各种民用与军用EMC标准的限值要求和测试方法。全书共分12章,内容包括:电磁兼容;电场与磁场、近场与远场、辐射体、感受器、天线;典型的噪声源及其辐射和传导发射特性;PCB印制线、导线、电缆间的串扰和电磁耦合;元件减小发射的方法及抗扰度;电磁屏蔽;电缆屏蔽、电场和磁场产生的耦合、电缆发射;接地和搭接;EMI测量、控制要求和测试方法;系统EMC和天线耦合;印制电路板;EMI和EMC控制、案例研究、EMC预测技术和计算电磁建模。此外,该书还为读者提供了一些可供选用的EMI诊断技术和费效比优良的解决方案。     

电磁兼容性与电磁无意干扰

N2001-06954 0103861电子情报通信学会技术研究报告:电磁兼容性 EM-CJ99-101～112(信学技报,Vol.99,No.528)[汇,日]/日本电子情报通信学会.—1999.12.—86P.(L)本文集收录12篇论文。内容主要涉及:IC/LSI的 EMC 特性测量时电源系统去耦的研究,多层印制电路衬底电源供给系统的2维分析,LSI 的 EMI 模拟用电源模型的研究,基于电流源的 IC 的电源端子电流的模型,磁场屏蔽效果测定法的计算模型,FET 输入型静电电压测量系统反应特性,电磁干扰电压的     

检测电缆故障点的电磁传感器设计与实现

电磁传感器是根据电磁感应原理用于检测电磁信号的。在精确检测电缆故障点时,根据故障点产生的磁场变化,电磁传感器拾取到这种变化的磁场信号,并将其转换成感应电压,感应电压经放大、整流处理后,用于后续检测指示电路,最后确定故障点的位置。     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

随机频率调制降低开关变换器电磁干扰的研究

利用随机频率调制技术从噪声产生源头上降低了开关变换器的电磁干扰。分析了具有不变概率密度分布的随机频率调制降低开关变换器EMI噪声的原理。将嵌入式系统产生的均匀分布离散随机信号加入脉宽调制芯片,开关频率随机变化,试制了一台随机频率调制开关变换器电源样机。给出了开关管电流信号的频谱以及传导干扰测试的结果。实验结果表明该技术能有效降低开关谐波峰值,使开关变换器易于通过EMI测试,具有应用前景。     

On the impact of on-chip inductance on signal nets under the influence of power grid noise

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence of power grid noise. The analysis is based on an Al-based 0.18-/spl mu/m CMOS process and a Cu-based 0.13-/spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology. A heuristic method is proposed in the paper to account for the inductive coupling due to power grid noise in signal delay modeling and simulations.     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

An integrated controller for tunnel sensors

Micromachined tunnel sensors require electronic circuitry to servo control their tunnel gap width. In this paper, we present the first integrated and complete tunnel sensor controller. This self-contained CMOS controller provides all necessary controller functions; it generates a tunnel junction bias, senses the tunnel current by dropping it across a diode-connected transistor, compares the voltage across this diode to an internally generated proportional to-absolute-temperature reference, derives a feedback signal with an externally configurable frequency response, generates a high-voltage electrostatic drive, and provides a low-voltage output for external circuitry. The chip requires -5 and -40-V power supplies and a compensation RC network, consumes 0.9 mW power, has a power supply rejection ratio of 30 dB, and has a total die area, exclusive of bond pads, of 0.35 mm². The circuit compensates for tunnel junction nonlinearity and contributes less signal noise than the sensor that it controls     

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance–inductance–capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.      

Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method

In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately.