MPEG-21在数字电视中的应用研究

MPEG-21多媒体框架是正在制订中的关于多媒体信息发布和使用的国际标准.研究了基于MPEG-21的数字电视系统的设计和实现及服务方式,分析了应用MPEG-21中定义的数字项来组织节目、传输和交互各类信息的可行性.     

多媒体框架标准MPEG-21

1999年提出的作为多媒体框架标准的MPEG—21目前也取得了重大进展，正引起人们的广泛关注。文中即对MPEC一21的目标、基本概念、关键要素、工作规划及应用领域等给予概括阐述。     

基于水印技术的MPEG-4形状错误隐藏

MPEG-4编码是一种基于对象内容的第二代视频编码方案,将视频根据内容分割成前景对象和背景。视频对象的信息分为形状信息、纹理信息和运动信息,而形状信息是正确解码视频对象的基础。本文就是针对MPEG-4编码标准中的I-VOP的形状信息的错误进行的错误隐藏。采用的方法有别于传统的曲线插值方法和马尔可夫域最大后验估计方法,首次采用基于鲁棒盲水印的算法,主要是将形状信息或变化作为水印信息嵌入到背景对象中。针对前人提出的方法只能修补小部分的损失,本文对于形状信息严重丢失的修复效果很好。     

An adaptive cross-layer mapping algorithm for MPEG-4 video transmission over IEEE 802.11e WLAN

This paper proposes an adaptive cross-layer mapping algorithm to improve the transmission quality of MPEG-4 video stream over an IEEE 802.11e wireless network. Instead of classifying video data to a specific access category in an 802.11e network, we propose an algorithm that dynamically maps MPEG-4 video packets to appropriate access categories according to both the significance of the video data and the network traffic load. Our proposed cross-layer architecture passes information about the significance of video packets from the application layer to the media access control layer. The queue length of a specific access category is used to deduce the network traffic load. We conducted a performance evaluation of our proposed cross-layer approach under both light and heavily loaded network conditions. Our simulation results demonstrate: (a) superior performance of our proposed approach (under both light and heavy loads) over 802.11e (Enhanced Distributed Channel Access (EDCA) and static mapping schemes, (b) not only guarantees prioritized transmission of essential video data but also provides efficient queue length utilization.     

一种低功率分层运动估值器的VLSI结构设计

本文提出一种新的低功率分层运动估值器的VLSI结构,它支持低比特视频编码器的高级预测模式,如H.263和MPEG-4。为减少芯片尺寸及功率消耗,在所有搜索层中使用同一个基本的搜索单元 (BSU)。另外,通过对数据流的有效控制,使其在高级预测模式下,在获得宏块运动矢量的同时,也获得每个宏块中的4个88子块的运动矢量。实验结果表明,这种结构采用较少的门电路,有效降低了功率消耗,并且实现了与全搜索块匹配算法(FSBMA)相似的编码效果,可广泛应用于无线视频通信所需的低功率视频编码器中。     

Everything you wanted to know about MPEG-7. 1

Audio-visual information must allow some degree of interpretation, which can be passed onto, or accessed by a device or a computer code. MPEG-7 aims to create a standard for describing these operational requirements. We provide an overview on the development, functionality, and applicability of MPEG-7. We present the role of MPEG-7 and outline ideas for using MPEG-7 technology based on examples of improved versions of existing applications as well as completely new ones. The MPEG standards preceding MPEG-7 have mainly addressed coded representation of audio-visual information. MPEG-7, on the other hand, focuses on the standardization of a common interface for describing multimedia materials (representing information about the content, but not the content itself (“the bits about the bits”)). In this context, MPEG-7 addresses aspects such as facilitating interoperability and globalization of data resources and flexibility of data management     

MPEG-2 video compression

MPEG-2 is an extension of the MPEG-1 international standard for digital compression of audio and video signals. MPEG-1 was designed to code progressively scanned video at bit rates up to about 1.5 Mbit/s for applications such as CD-I (compact disc interactive). MPEG-2 is directed at broadcast formats at higher data rates; it provides extra algorithmic 'tools' for efficiently coding interlaced video, supports a wide range of bit rates and provides for multichannel surround sound coding. This tutorial paper introduces the principles used for compressing video according to the MPEG-2 standard, outlines the general structure of a video coder and decoder, and describes the subsets ('profiles') of the toolkit and the sets of constraints on parameter values ('levels') defined to date.     

An interoperable delivery framework for scalable media resources - seamless content delivery in the future mobile internet

In this article an interoperable framework for the delivery of scalable media resources (e.g., in the standardized scalable video coding format) is presented. The framework provides support for video on demand as well as multicast streaming, and performs efficient, generic, and interoperable adaptation of streamed content based on MPEG- 21 Digital Item Adaptation. The server as well as the clients of the streaming framework implement the MPEG Extensible Middleware and utilize the MPEG Query Format for querying the available media resources. The framework has been fully integrated into the VLC media player. The architecture for both VoD and multicast is presented in detail. Finally, a comparison in terms of performance of the generic MPEG-21 metadata-based adaptation approach to an SVC-specific adaptation approach is provided.     

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

MPEG-4概述

从ISO/IEC14496的第一部分MPEG-4系统的体系结构出发,分别对MPEG-4标准中提供的主要工具进行了技术描述,包括对象描述框架、系统解码器模型(SDM)和传输多媒体集成框架(DMIF)、场景的二进制描述(BIFS)、同步层、视频对象和音频对象编码等.最后对MPEG-4系统的特性做出了小结并探讨了该标准的应用前景.     

Subjective evaluation of MPEG-4 video codec proposals: Methodological approach and test procedures

A new audio-visual coding standard, MPEG-4, is currently under development. MPEG-4 will address not only compression, but also completely new audio-video coding functionalities related to content-based interactivity and universal access. As part of the MPEG-4 standardization process, in November, 1995 assessments were performed on technologies proposed for incorporation in the standard. These assessments included formal subjective tests, as well as expert panel evaluations. This paper describes the MPEG-4 video formal subjective tests. Since MPEG-4 addresses new coding functionalities, and also operates at bit-rates lower than ever subjectively tested before on a large scale, standard ITU test methods were not directly applicable. These methods had to be adapted, and even new test methods devised, for the MPEG-4 video subjective tests. We describe here the test methods used in the MPEG-4 video subjective tests, how the tests were carried out, and how the test results were interpreted. We also evaluate the successes and shortcomings of the MPEG-4 video subjective tests, and suggest possible improvements for future tests. The MPEG-4 video subjective tests were successful, providing the MPEG community with critical information to guide in the selection of technologies for inclusion in the video part of the MPEG-4 standard.     

发展中的MPEG-21标准及其应用

介绍了多媒体框架国际标准MPEG—21的体系结构、主要内容和核心技术，讨论了使用MPEG—21在异构网络环境中进行综合多媒体访问的技术。     

Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations

MPEG-4 is a new multimedia standard combining interactivity, object-based natural and synthetic digital video, audio and computer-graphics. For the implementation of the video part of the MPEG-4 standard a high degree of flexibility is required, where the motion estimation requires the highest part of the computational power. Therefore, in this paper fast algorithms for MPEG-4 motion estimation are evaluated in terms of visual quality and computational power requirements for processor based implementations. Due to the object-based nature of MPEG-4 also new VLSI architectures for MPEG-4 motion estimation are required. Therefore known motion estimation architectures are evaluated on their capability of being modified for MPEG-4 support. Based on this evaluation a new dedicated, but flexible MPEG-4 motion estimation architecture targeted for low-power handheld applications is presented, which resulted to be advantageous to processor based implementations by magnitudes of order.     

MPEG-4中基于DT网格编码算法的实现

本文按照MPEG-4标准对DT网格对象编码的要求,设计了一套完整的基于DT网格的编码算法.首先提出了网格对象编码的系统框架.在此基础上,着重研究了网格运动编码,提出了一种新的三角形运动连续预测方法及相应的残差图像处理方法.最后,对整个数据结构进行转换,使之完全按照标准规定的顺序进行编码.本文算法同H.263进行了全面的比较.结果表明,DT作为MPEG-4标准中的一种编码方法,有一定的实用价值.     

An MPEG-4 Renderer for High Quality Video Composition and Texture Mapping

This paper presents the hardware architecture of a co-processor supporting the real time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It enables the composition and the transformation of natural video objects and the texture mapping on triangles, allowing the 2D-mesh decoding. This architecture is able to render scenes that are compliant with MPEG-4 Main Profile, Level3 and Hybrid Visual Profile. The co-processor is designed to be used in a shared memory system architecture. It consists in a dedicated implementation that seeks the best compromise between cost and performances. In a first step, a software model is used to guarantee the visual quality of the rendered scene and to validate the algorithmic choices. Then, the complexity and performances of this novel architecture are evaluated. Finally, a behavioral model validates the architectural choices.     

用于H.264编解码的面向HDTV应用的动态可重构多变换VLSI结构

提出了一种新的支持MPEG-4 AVC/H.264标准4×4整数变换的动态可重构结构.首先,针对4×4正反变换分别推导了两个新的二维直接信号流图.进而设计了一个面向HDTV应用的动态可重构多变换结构.该结构无需转置寄存器且计算单元仅需16个加法器(减法器).采用0.18μm CMOS工艺实现了该电路结构.结果表明,最高...     

A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm

Image feature separation is a crucial step for image segmentation in computer vision systems. One efficient and powerful approach is the unsupervised clustering of the resulting data set; however, it is a very computationally intensive task. This paper presents a high-performance architecture for unsupervised data clustering. This architecture is suitable for VLSI implementations. It exploits paradigms of massive connectivity like those inspired by neural networks, and parallelism and functionality integration that can be afforded by emerging nanometer semiconductor technologies. By utilizing a "global-quasi-systolic, local-hyper-connected" architectural approach, the hardware can process real-time DVD-quality video at the highest rate allowed by the MPEG-2 standard. The architecture is a realization of the histogram peak-climbing clustering algorithm, and it is the first special-purpose architecture that has been proposed for this important problem. The architecture has also been prototyped using a Xilinx field programmable gate array (FPGA) development environment. Although this paper discusses a computer vision application, the architecture presented can be utilized in the acceleration of the clustering process of any type of high-dimensionality data.     

Platform-independent MB-based AVS video standard implementation

AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization.