广域分组无线网及其自适应技术支持

广域分组无线网及其自适应技术支持罗翔分组无线网（ＰＲｎｅｔ）是日渐发展的一种利用无线信道传输信息的分组交换通信网络。它提供了使用无线多址信道方法，来支持计算机之间、数据终端之间或计算机与数据终端之间的通信及信息的收集与分配。与电路交换相比，分组交换能...     

FDM信道传输特性对数据通讯质量的影响

随着我国数据通讯事业的发展,数据传输设备和数据终端的不断完善,人们已不在满足于原来的点——点数据通讯的要求,为了互通情报、交换和收集数据等目的,各种数据通讯网建立已势在必行.在这建网的过程中,除了合理地考虑网络结构形式、交换方式、网络规模和功能、规程选用以及设备的组成而外,还必须对传输数据的媒介——通讯信道给予足够的重视.通讯信道质量的好坏是建设各种网络的物质基础,对此各国都投入了大量的人力和经费对现有信道加以改造,以期符合数据通讯的     

多串口并行通信数据传输系统设计

传统多串口并行通信数据传输系统无法自主获取串口号,需手动选择再打开串口,需要使用者事先了解接口编码,这无形增加了系统的工作时间。为此,设计一种基于FPGA的多串口并行通信数据传输系统,该系统中的串口数据接收模块采集多串口数据,并通过控制寄存器达到控制通信数据波特率的目的。系统利用NiosⅡ处理器使8种信道共同进行传输工作,其将数据传输到并串转换模块。并串转换模块对输出的8位并行数据添加通道标识、并串转换处理,再将处理后的并行数据传递到串口输出选择模块中。依据数据脉冲上升沿设计串口输出选择模块,该模块通过多路分配器将有数据通道的数据串行逐位送出。系统在软件中进行了传输设计、NiosⅡ处理器流程设计以及通信设备类的设计与封装。实验结果表明,所设计系统在FPGA上正确实现了8个串口数据的传输,并且具有较高的数据接收成功率。     

一种信道串口检测平台设计实现

在卫星通信链路中,串口通信故障往往涉及多个设备,若不能准确定位故障点,将影响通信任务执行。本文为快速定位串口通信问题,在研究串口通信模式和通信协议基础上,选取适当硬件模块,设计相应控制软件,搭建串口检测平台,将信道设备与检测平台进行连接和测试,实现待测设备性能评估和串口状态诊断功能,为快速处置设备问题、提升设备维护效率提供支持。     

数据通信设计指南(1)

由爱伦丁、惠斯勃格(AlanJ,Weissberger)撰写的五篇有关数据通信的连载分别刊于《电子设计》1979年卷27第9、10、12、15和17号上。第一篇介绍了通信信道和传输设备的特性;第二篇重点讨论了模拟信道中数字信息传输的变换以及完成此类变换的调解器、数据装置等硬件的作用;第三篇阐述了数据终端和数据通信设备间的界面接口,其中包括接收机/发送机电路(特别是大规模集成电路片子)、同步及管理线路和设备连结的各种标准和规定;第四篇则叙述了数据链路控制(特别是大规模集成链路控制片)以及其对分布处理网络结构的影响;第五篇简介了一些规划和实现的公用及专用数据网的情况。     

基于5G的多机器人协同技术研究

随着 5G、大数据、云计算、物联网以及人工智能等技术的蓬勃发展，多机器人应用场景越来越多的出现在人类的生产和生活中。针对多机器人协同通信时易产生的信道碰撞问题和通信协议不一致导致的无法互通问题，提出了改进型指数递增指数递减退避算法(IEIED)和基于 5G 通信的云平台信息交换技术，能够有效降低多机器人通信的信道碰撞概率，提高信道接入的公平性，提高网络吞吐量，减小数据传输的时延；利用云平台信息交换技术将数据处理、数据共享、数据融合等都集中在云端，可以大幅简化用户终端的设计，只需使用通信模块将机器人接入云平台即可实现各种机器人之间的互联互通。     

多信道光纤开关

美国DiCon Fiberoptics Inc.新近推出一种便携式多信道光纤开关,它具有1×N和2×N两种结构,最大信道数达40。单模(或多模)光纤-光纤能精确对位,典型损耗低到     

宽带化的VSAT卫星通信

甚小口径卫星通信终端(VSAT,Very Small Aper-ture Terminal)是20世纪80年代中期开发的一种新的卫星通信系统。利用这种系统进行通信具有灵活性强、可靠性高、成本低、使用方便以及小站可直接装在用户端等特点。借助VSAT,用户数据终端可直接利用卫星信道与远端的计算机进行联网,完成数据传递、文件交换或远程处理,从而摆脱本地区的地面中继线问题。在地面网络不发达、通信线路质量不好或难以传输高速     

基于V-MIMO系统的信号检测与最优权值搜索

介绍了虚拟多输入输出(V-MIMO)系统中在一根天线上发射多路信号时的信道估计、信号检测方法与最优权值的搜索算法。V-MIMO系统采用最小均方(LMS)算法2次进行信道估计,防止一帧数据中信道衰弱造成的信道估计误差,保证了信道估计的准确性;V-MIMO系统采用最大似然(ML)检测算法,提高了检测的准确性,降低了误码率;同时采用遍历和变步长breaklocal算法,分别针对较少用户和较多用户数据传输的情况搜索最优权值,降低了系统的计算复杂度。在2×2,1×2,2×3,2×4的实际测试中,在不增加功率和带宽的基础上,V-MIMO系统传输效率至少提高了70%,同时减少了发射天线的数量。     

多功能智能通信控制器

本文介绍了一种可编程、多规程智能通信控制器。该通信控制器采用PC总线插板式结构、以双端口RAM与通信计算机进行信息交换。其优点是不占用主机任何资源、信息交换速度快;具有链路控制智能化,信息传输智能化,数据、话音兼容等特点。在点对多点、多信道通信系统中,这种智能通信控制器更显其优越性。     

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil²and the total chip size is 218 × 235 mil². The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.     

Study of a SiGe-HBT-based 1：2 demultiplexer IC up to 100 Gb/s rate

An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis sho...     

A monolithic light-emitting-diode display

A monolithic 5 × 7 array of planar diffused p-n junctions in GaAs1-xPx(x≃0.38) has been built for a light-emitting diode (LED) alphanumeric readout. A character formed by this readout is 0.246 cm high and 0.170 cm wide. The monolithic chip has all p-n junctions, n-contacts, p-contacts, interconnections and terminal metallurgy on the epitaxial layer which represents a departure from the conventional methods of making LED arrays, namely wire bonding discrete chips with contacts on two sides in a hybrid configuration. Each LED in the array is connected to one of the terminals arranged around the periphery of the chip and individually addressed by direct current from a driver on a silicon control chip. For each character position in a display there is one monolithic LED chip and one monolithic silicon control chip solder joined to terminals on a glass plate and interconnected by Cr-Cu-Cr lines evaporated onto the glass substrate. The display is addressed by serial information provided from an ROM which is read into a 35-stage shift register on the control chip which controls the drivers. Thus with two standard parts, any N-character display can be fabricated with considerable reduction in handling since no discrete elements or wire bonds are used.     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

基于AT89C51单片机的RS232串行数据截取器设计

为了实现对RS 232串行通信数据的截取,给出了基于AT89C51单片机的设计方案。系统利用GM8123芯片将单片机的1个串口扩展成为3个串口,采用MAX232芯片实现RS 232电平与TTL电平之间的相互转换,单片机通过串行口截取通信数据并对数据进行处理,处理后的数据再通过串行口发送到上位机进行显示。该系统具有两种工作模式,模式1实现对通信数据的实时截取,模式2是采用存储转发原理,截取器可以脱离上位机而工作。     

嵌入式系统中实时时间的获取

针对在嵌入式系统中,当系统重启或异常断电的情况下,实时时间信息丢失的问题,本文提出了两种获取实时时间的方法：时钟芯片方法和GPS方法。时钟芯片方法中以DS1302为例,介绍了它在嵌入式系统中的软硬件设计。GPS方法中使用6PS接收机接收卫星信号,然后将符合NMEA-0183协议的格式化数据通过串口送往嵌入式系统,再通过软件提取数据中的时间信息。     

Area-efficient multi-channel active matrix micro-LED driver chip design

This study develops the control and driver for active Micro LED panel with chip-level design. The chip includes constant current circuit, digital-to-analog converter, SPI control interface, and active-matrix display control. The design process uses TSMC0.18um HVG2 CMOS technology, to realize 30 channels for micro LED driver. To reduce I/O pins, the input signals feed to the dynamic shift register in serial, and the results are loaded to the digital-to-analog converter (DAC) in parallel. The DAC module consists of R2R network, unity-gain buffer and sample-and-hold circuits. The DAC outputs with constant current for micro LED driving from voltage-to-current conversion. To reduce the number of DAC component, one DAC can share the common circuit to drive RGB LED of one pixel based on the selected current mirror structure. This chip can greatly reduce resistor and switches about 92% and 96% respectively, compared with the conventional R DAC structure. The measurements result with good linear for the current dimming control, which the test digital signals are generated by Verilog codes to estimate the gray current of this chip.

     

PC机与DSP异步串口通信实现研究

以美国TI公司的TMS320C5410DSP芯片为例,介绍DSP片内多通道缓冲同步串口接口(McBSP)的结构特点、针对用户经常面临的DSP系统与PC机实时交换数据时通信接口标准不兼容的问题,提出了一种新的串行通信设计方案,实现了DSP同步串口McBSP与PC机异步串口RS-232的全双工通信。     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.