A CMOS double-heterodyne FM receiver

Experimental results for a narrow-band, adjustment-free double-heterodyne CMOS FM receiver with a high-Q switched-capacitor IF filter centered at 3 MHz are presented. The integration covers all the filtering and demodulation circuits from radio-frequency circuits (50-100 MHz) to the audio output. An experimental prototype FM receiver exhibiting a 5-mV input sensitivity and a -30-dB quieting level is implemented using 1.75-/spl mu/m double-poly CMOS technology. The chip occupies 7.7 mm and dissipates 80 mW with a 5-V supply.     

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.     

Multichip optical transmitter module for chip-to-chip interconnection on optical PCBs

A multichip module of an optical transmitter, which consists of flip-chip bonded 1/spl times/4 VCSELs on a CMOS driver array IC, is fabricated and demonstrated. The -3 dB bandwidth and adjacent crosstalk of the hybrid integration multichip module are about 4.5 GHz and less than -30 dB, respectively. The whole integrated multichip volume is 1.1/spl times/1.2/spl times/0.52 mm/sup 3/ for four channels.     

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew

A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.     

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.     

A pulse position modulation transmission system for remote control of a TV set

A transmitter-receiver combination for remote control of a color TV set is described. The transmitter is a 1.6/spl times/1.9 mm/SUP 2/ chip in linear bipolar technology. It generates a 5-bit PPM code for transmission of 32 commands, requires only 5 external components and an 8/spl times/4 single-pole single-throw keyboard. Standby power is zero. The receiver is a 3.1/spl times/3.5 mm/SUP 2/ p-MOS chip and allows for a 20-channel selection. It has 3 D/A converters on chip to generate the analog control signals. It also controls the TV receivers AFC and on-screen display.     

A novel bidirectional CMOS transceiver for chip-to-chip optical interconnects

A novel bidirectional complementary metal-oxide-semiconductor (CMOS) transceiver for chip-to-chip optical interconnects operating at 2.5 Gb/s is proposed, which shares the common block of a receiver and a transmitter on a single chip. The share of the common block of two circuits makes it possible to save 55% or 20% of power dissipation, depending on the operating mode. The chip in 0.18-/spl mu/m CMOS technology occupies an area of 0.82/spl times/0.82 mm/sup 2/, 70% of the total area of a typical unshared transceiver chip. The transmitting and receiving modes of operation show -3-dB bandwidths of 2.2 and 2.4 GHz and electrical isolations of -28 and -40 dB, respectively.     

A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

A CMOS ultra-wideband impulse radio (UWB-IR) transceiver was developed in 0.18-/spl mu/m CMOS technology. It can be used for 1-Mb/s data communications as well as for precise range finding within an error of /spl plusmn/2.5 cm. The power consumptions of the transmitter and receiver for data communication are 0.7 and 4.0 mW, respectively. When an LNA operates intermittently through bias switching, the power consumption of the transceiver is only 1 mW. The range for data communication is 1 m with BER of 10/sup -3/. For ranging applications, the transmitter can reduce the power to 0.7 /spl mu/W for 1k pulses per second, and the receiver consumes little power. The transceiver design, all-digital transmitter, and intermittent circuit operation at the receiver reduce the power consumption dramatically, which makes the transceiver well suited for applications like sensor networks. The electronic field intensity is lower than 35 /spl mu/V/m, and thus the UWB system can be operated even under the current Japan radio regulations.     

Parallel-optical interconnects >100 gb/s

A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s giving an aggregate data rate of 102 Gb/s is demonstrated, to the authors' knowledge, for the first time. The paper describes and demonstrates 13 /spl times/ 16-mm cross-section 12-channel parallel-optic transmitter and receiver modules with each channel operating at a data rate of 8.5-10 Gb/s. This was achieved using bottom-emitting 990-nm vertical-cavity surface-emitting lasers and bottom-illuminated InGaAs-InP photodetectors flip-chip bonded directly to 12-channel transmitter and receiver integrated circuits, respectively. In addition, 102-Gb/s link results are demonstrated over 100 m of 50-/spl mu/m-core standard multimode ribbon fiber. A bit-error ratio of <10/sup -13/ was measured on a single channel after transmission through 100 m of multimode fiber at a data rate of 8.5 Gb/s with all 12 channels operating simultaneously.     

A wideband frequency-shift keying wireless link for inductively powered biomedical implants

A high data-rate frequency-shift keying (FSK) modulation protocol, a wideband inductive link, and three demodulator circuits have been developed with a data-rate-to-carrier-frequency ratio of up to 67%. The primary application of this novel FSK modulation/demodulation technique is to send data to inductively powered wireless biomedical implants at data rates in excess of 1 Mbps, using comparable carrier frequencies. This method can also be used in other applications such as radio-frequency identification tags and contactless smartcards by adding a back telemetry link. The inductive link utilizes a series-parallel inductive-capacitance tank combination on the transmitter side to provide more than 5 MHz of bandwidth. The demodulator circuits detect data bits by directly measuring the duration of each received FSK carrier cycle, as well as derive a constant frequency clock, which is used to sample the data bits. One of the demodulator circuits, digital FSK, occupies 0.29 mm/sup 2/ in the AMI 1.5-/spl mu/m, 2M/2P, standard CMOS process, and consumes 0.38 mW at 5 V. This circuit is simulated up to 4 Mbps, and experimentally tested up to 2.5 Mbps with a bit error rate of 10/sup -5/, while receiving a 5/10-MHz FSK carrier signal. It is also used in a wireless implantable neural microstimulation system.     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Passively assembled optical interconnection system based on an optical printed-circuit board

We propose a passively assembled chip-to-chip optical interconnection system using fiber-optic technology. To demonstrate the system, three components were prepared: a fiber-embedded optical printed-circuit board (OPCB), optical transmitter/receiver modules, and 90/spl deg/-bent fiber connectors. All components were assembled using precise guide pins and holes so that complete passive alignment was achieved in the OPCB. An optical link of 5-Gb/s/ch signals with a total link loss of -1.5 dB has been successfully demonstrated from the assembled system.     

Parallel optical interconnection for uncoded data transmission with1 Gb/s-per-channel capacity, high dynamic range, and low powerconsumption

The design, realization, and characterization of a multichannel dc-coupled ECL-voltage compatible parallel optical interconnection with a bit rate of up to 1 Gb/s-per-channel is reported. The transmitter module consists of an array of laser diodes with low threshold currents and the 50 Ω matching network, the receiver module of a photo diode array and an amplifier array. All the opto-electronic and electronic components are fabricated as arrays with a pitch of 250 μm. The total power consumption is 110 mW per channel, For a BER <10¹⁴ the dynamic range is 15 dB for a bit rate per channel of 200 Mb/s, 13 dB for 630 Mb/s, and 8 dB for 1 Gb/s. The channel crosstalk is below -48 dB (electrical). The size of the opto-electronic parts (12 channels, without electrical connectors) is only 10 mm (length)×5 mm (width)×4 mm (height)     

An analog front-end chip set employing an electro-optical mixeddesign on SPICE for 5-Gb/s/ch parallel optical interconnection

A chip set composed of a laser-diode driver (LDD) and an optical receiver (RCV), which incorporates a full 2D (reshape, regenerate) function, has been developed by using silicon bipolar technology for a four-channel 5-Gb/s parallel optical transceiver. An electro-optical mixed design on SPICE of the LDD and the LD is accomplished by describing the rate equations of the LD as an electrical circuit. This design accommodates easy connectivity of the LDD chip to the LD in the optical transmitter module without the need for adjustment of the optical waveform. A pseudobalanced transimpedance amplifier (TIA) and feedforward automatic decision threshold control (ATC) in the RCV minimize the number of off-chip bypass capacitors, eliminate the need for any off-chip coupling capacitors, and keep crosstalk less than -50 dB and low cutoff frequency less than 80 kHz. A prototype parallel optical transmitter module and a prototype receiver module, based on the chip set, demonstrated asynchronous four-channel 5-Gb/s operation. The chip set has a throughput of 20 Gb/s with a power dissipation of 1.3 W at a 3.3-V supply     

High-efficiency 1.3 /spl mu/m InAsP-GaInP MQW electroabsorption waveguide modulators for microwave fiber-optic links

High-efficiency electroabsorption waveguide modulators have been designed and fabricated using strain-compensated InAsP-GaInP multiple quantum wells at 1.32-/spl mu/m wavelength. A typical 200-/spl mu/m-long modulator exhibits a fiber-to-fiber optical insertion loss of 9 dB and an optical saturation intensity larger than 10 mW. The 3-dB electrical bandwidth is in excess of 20 GHz with a 50-/spl Omega/ load termination. When used in an analog microwave fiber-optic link without amplification, a RF link efficiency as high as -38 dB is achieved at 10 mW input optical carrier power. These analog link characteristics are the first reported using MQW electroabsorption waveguide modulators at 1.32 /spl mu/m.     

2.5 Gbit/s multifunctional CMOS transceiver for chip-to-chip optical link

A novel multifunctional transceiver for chip-to-chip optical interconnects operating at 2.5 Gbit/s is proposed, which shares a common block between a receiver and a transmitter. This transceiver provides four conversion functions - electrical-to-optical, optical-to-optical, optical-to-electrical, and electrical-to-electrical - depending on the selection switch on a single chip. The whole chip integrated in 0.18 /spl mu/m CMOS occupies an area measuring 0.82/spl times/0.82 mm/sup 2/.     

Embedded TiNxOy thin-film resistors in a build-up CSP for 10 Gbps optical transmitter and receiver modules

Integral passive components provide efficient circuit miniaturization while maintaining high performance and reducing assembly costs. The development of practical integral passive components, however, requires advances in the areas of materials, low-cost processes, and structural design. We have developed new TiNxOy thin-film resistors, as well as a termination resistor-embedded CSP, and a process for fabricating integral passive components. Our TiNxOy films exhibit a sheet resistivity in the range of 30-5k /spl Omega//square. To keep costs low, we have made the fabrication process compatible with that for MCM-D/L. Resistors as small as 25 /spl mu/m square have been successfully produced with this process. The chip scale package (CSP) with embedded resistors has been designed for 10 Gbps optical transmitter and receiver modules. A fabricated version shows excellent return loss for its termination resistor, less than -20 dB in the frequency range of 50 MHz-14 GHz, and its resistors showed high reliability in constant voltage stress tests, with less than 5% change in resistance at 800 mW/mm/sup 2/ over 1000 hours.     

An Energy-Efficient OOK Transceiver for Wireless Sensor Networks

A 1-Mb/s 916.5-MHz on-off keying (OOK) transceiver for short-range wireless sensor networks has been designed in a 0.18-mum CMOS process. The receiver has an envelope detection based architecture with a highly scalable RF front-end. Untuned RF circuits are leveraged and optimized in the receiver to achieve superior energy efficiency compared to tuned RF circuits. The receiver power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10 ^-3. The transmitter consumes 3.8 mW to 9.1 mW with output power from -11.4 dBm to -2.2 dBm. The receiver achieves a startup time of 2.5 mus, allowing for efficient duty cycling     

3.5-Gb/s×4-ch Si bipolar LSI's for optical interconnections

The 3.5-Gb/s, 4-ch transmitter and receiver LSI's described here include a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circuits that can generate high-speed clock (3.5 GHz) and retimed data. The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL. Both the transmitter and receiver LSI are 4.5-mm-square and are fabricated by a 40-GHz 0.5-μm Si bipolar process. The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W. Both have -4.5- and -2-V supply voltages