估算高稳时钟抖动的幂率积分下限的研究

 幂律积分法是估算亚皮秒级时钟信号抖动所采用的一种常用方法.该方法的换算结果与积分区间有关,尤其与积分下限有关.通过对幂律积分法将相位噪声转换为抖动的关系式介绍,推导了幂律积分下限与采样时钟的频率、被采样模拟信号的最高频率及A/D变换的有效位之间的关系,给出了估算幂律积分下限的算式,并提供了该算式在估算中频采样系统时钟信号抖动中的应用实例,间接证明了该算式.     

高性能中频采样系统的设计与实现

为提高中频采样系统性能,降低板级噪声,加大采样频率的灵活性,设计并实现一种高性能中频采样系统.该系统利用AD9518-4实现可配置的采样时钟,根据不同的采样要求,AD9518-4可提供多路不同频率的输出.系统还采用AD8352型运算放大器作为A/D转换器前端驱动电路,将单端中频输入信号转换为差分信号,并进行相应放大,滤波等工作.配合AD9445型A/D转换器.获得14位低电压差分输出信号.实验结果表明,该系统在40 MHz中频信号输入的情况下,信噪比达到77.4 dBFS,并可实现采样时钟的可编程配置.与传统方案相比,该采样系统信噪比、无杂散动态范围,有效比特位等性能指标都得到明显改善.     

中频数字信号处理系统中采样时刻抖动特性分析

中频数字信号处理系统中,采样时刻抖动是决定系统功能成败与指标好坏的关键。文章中分析了采样时刻抖动对中频数字信号处理系统信噪比的影响,并给出了比以往文章中更准确的计算公式;分析了采样时刻抖动的形成因素,并介绍了采样时刻抖动的测量和计算方法。该方法可以直接利用采样系统实施ps级的抖动测量,不需要特殊仪器设备。     

DBF合成中高速数据采样的抖动对波束形成的影响

主要讨论了采样抖动对中频信号信噪比的影响,提出了一种采样抖动对信噪比影响的数学分析方法。对由于采样抖动使得各路ADC的采样不同步对波束形成造成的影响进行了定量的仿真分析。     

采样时钟抖动在弱光信号检测中的影响分析

信号采样是弱光信号检测的关键技术环节,由于采样时钟抖动引起的采样信号的输出误差会影响后续的信号检测和处理。为此,分析了输入光信号为近高斯分布波形时由时钟抖动引起的采样误差,推导出了采样输出的信噪比损失公式,讨论了采样带宽、输入信噪比以及信号脉宽对输出信噪比损失的影响,最后以取样积分检测技术为对象,计算了在不同累积次数的条件下采样抖动对取样积分检测性能的影响,对弱光信号检测中的采样时钟选取具有一定的指导意义。     

一种新的中频采样滤波器的设计与实现

许多信号处理算法是针对复信号的,因此,从实带通信号中产生复信号是信号处理中的一个重要问题.中频采样技术是对中频信号直接采集产生正交复基带信号的技术,一般是采用2b或4b采样频率(b为信号带宽),而且滤波器的系数是以表格形式给出的,因此使用者不能根据实际情况对滤波器加以修正.本文提出了一种新的滤波器设计方法,它没有限定采样频率和信号带宽之间的关系,换句话说,信号的归一化带宽是可变的.此外,新滤波器的系数是以解析形式表示的,可以方便地根据实际信号的带宽计算出最佳滤波器的系数.当信号带宽较窄时,新滤波器的性能明显优于现有滤波器.文章的最后介绍了一种基于SHARC的中频采样的实现方案.该方案已经用于实际系统,取得了很好效果.     

一种新型无人机高分SAR 信号非均匀混合采样技术

无人机高分辨合成孔径雷达(SAR)系统具有较大的信号频率带宽,根据奈奎斯特采样定律,雷达接收机需要超高速采样的ADC芯片。由于超高速采样率的ADC芯片的采样量化位数较低、功耗较高、成本昂贵,直接采用超高速采样ADC芯片对无人机高分辨率SAR回波信号进行采样接收不是最优方法。文中提出一种新型的非均匀混合采样技术用于对无人机高分辨率SAR回波信号进行采样接收,通过优化无人机SAR系统的信号收发时序,利用325 Msps采样率的ADC芯片即可对频率带宽为2 GHz的雷达回波信号进行采样接收,保证雷达回波的相位扰动与旁瓣电平满足应用需求。仿真实验表明:2 GHz带宽的Ku-SAR系统的回波信号能被采样率为325 Msps的ADC芯片完好采样接收,成像分辨率优于0. 2 m,旁瓣电平控制在-13 dB以下。     

一种超宽带光电混合结构A/D转换器

现代宽带数字接收机对高性能模数转换器(ADC)的需求逐渐增大,而电子学ADC因载流子迁移速率限制无法实现超宽带直接数字采样。基于光子技术超宽带、超高速的特性,文章提出了一种光电混合结构的ADC技术。通过采用基于超短光脉冲的光学采样代替基于电子学半导体技术的采样/保持(S/H)电路来大幅提高采样带宽。采用时分复用及多通道电学ADC量化技术实现信号数字编码。最后通过数字域均衡与线性化处理提高系统性能,实现了对频率大于24 GHz的微波信号的直接采样,采样信噪比大于40 dB,为超宽带微波信号高精度直接数字化提供了有效途径。     

基于光采样的瞬时测频技术研究

传统高频微波信号瞬时测频(Instantaneous Frequency Measurement,IFM)技术受模拟数字转换器(Analog To Digital Converter,ADC)影响很大.提出了一种新的光采样方法,放弃传统的ADC,利用光强度调制器将高频微波信号调制到低重复频率采样光脉冲上,进而达到光采样的目的.利用快速傅里叶变换(Fast Fourier Transform,FFT)结合线性调频z变换(Chirp-z Transform,CZT)的方法,提高频谱分辨率,对欠采样条件下产生的频率余数进行准确估计,进而通过中国余数定理对信号频率进行重构.实验模拟表明,该方法可以对39GHz带宽内信号频率进行准确测量.     

宽带数据采集系统的相位噪声分析

研究了宽带数据采集系统的相位噪声、信号频率和信噪比之间的关系。根据相位噪声的计算模型,推导出多载频信号和宽带信号相位抖动信噪比的计算方法,通过噪声的频谱可以看出,独立时钟相位的抖动噪声是均匀分布在整个采样频谱中的,过采样和滤波可有效改善其信噪比。理论结果表明线性调频信号的相位噪声可用宽带信号的模型计算,当信号的带宽较小时,完全可由单频信号的计算公式得出近似的结果。最后,仿真结果验证了该SNR算法的有效性。     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

基于24 GHz FMCW 雷达的二维近场成像系统

为进行隐藏危险金属制品的安检,文中提出了一种24 GHz 低成本毫米波成像系统。该系统采用低成 本24 GHz 商用调频连续波(FMCW)雷达作为扫描源,在方位角和仰角上合成大孔径,使用二维十字扫描平台,经 FMCW 雷达信号处理以及合成孔径雷达(SAR)处理使隐藏物体成像。低成本的射频外设只提供了一路中频实信号 供ADC 采样量化,在图像重建中,文中提出将单路ADC 采样量化后的中频数字信号通过希尔伯特变换成复信号,对 复信号加布莱克曼窗优化频谱,再对信号序列补零以减小频域栅栏效应,后采用空间匹配滤波器补偿相位偏差,通 过FMCW 雷达近场成像原理对目标成像。改进后的算法适用于低成本的雷达前端系统,只需一路ADC 采集的中频 数字信号即可使成像系统达到理论的合成孔径成像分辨率。     

软件无线电中信号中频与采样频率选择

研究了在软件无线电中如何选择合适的信号中心频率与相应的采样频率,在经典的信号带通采样技术基础上对信号带宽和采样频率的关系加以讨论,确定了选择采样频率及信号中心频率的方案,并得到了最大的保护带宽,最后给出了具体工程算例,其研究结果对设计相应的软件无线电平台具有实际的指导价值。     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

一种高线性度CMOS自举采样开关

作为ADC系统与外界的接口,采样开关的性能优劣直接决定了ADC所接收到的信号纯度和真实性。高线性度的CMOS开关可在极大程度上抑制采样时间不确定、时钟馈通和电荷注入等非线性误差。文章首先讨论了MOS采样开关非线性的来源和互补型CMOS采样开关的不足之处,然后设计实现了一种高线性度CMOS自举采样开关。仿真结果表明所设计的高线性度CMOS自举开关的SFDR达101.5dB,可以适用于16位精度的ADC应用要求。     

Identification of cubically nonlinear systems excited by bandpass inputs

Identification of cubically nonlinear systems excited by bandpass inputs using discrete-time samples of the input and output signals is investigated. When excited by a bandpass signal, a nonlinear system may generate an output signal which occupies multiple frequency bands. Therefore, although the input signal can be bandpass sampled without causing aliasing by following the well known bandpass sampling theorem, the output signal must obey more sophisticated bandpass sampling criteria to avoid aliasing. Specifically, when a cubically nonlinear system is excited by a bandpass input signal whose highest frequency is larger than three times its bandwidth, a proper bandpass sampling frequency without causing aliasing in the sampled output signal must be at least 18 times the bandwidth of the input signal. First, a method for identifying the cubically nonlinear system using properly bandpass sampled data is developed. Then, a novel method is proposed, which allows identification of the cubically nonlinear system using data sampled at about twice the bandwidth of the input signal, even though aliasing exists in the sampled output under these circumstances. Compared to conventional methods, the proposed methods have the advantage of requiring a lower sampling rate. This makes the proposed methods highly appreciated in situations where high-speed sampling is unattainable.     

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

强干扰情况下用于CDMA系统的时空域联合处理

本文提出了一个时空域联合处理技术来对抗码分多址通信系统中的多址干扰.它由智能天线和多用户联合检测结合而成,智能天线可以压制与有用信号来向不同的干扰,余下的与用户信号来向相同的干扰可以被多用户联合检测系统消除.这种结构在干扰严重的信道仍能得到令人满意的效果.     

Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.