Ferroelectricity in Polar Polymer‐Based FETs: A Hysteresis Analysis

There is an increasing number of reports on polar polymer‐based ferroelectric field effect transistors (FeFETs), where the hysteresis of the drain current–gate voltage (I_d–V_g) curve is investigated as the result of the ferroelectric polarization effect. However, separating ferroelectric effect from many of the factors (such as charge injection/trapping and the presence of mobile ions in the polymer) that confound interpretation is still confusing and controversial. This work presents a methodology to reliably identify the confounding factors which obscure the polarization effect in FeFETs. Careful observation of the I_d–V_g curves, as well as monitoring the I_d–V_g hysteresis and flat band voltage shift as a function of temperature and sweep frequency, identifies the dominant mechanism. This methodology is demonstrated by using 15 nm thick high glass transition temperature polar polymer‐based FeFETs. In these devices, room temperature hysteresis is largely a consequence of charge trapping and mobile ions, while ferroelectric polarization is observed at elevated temperatures. This methodology can be used to unambiguously prove the effect of ferroelectric polarization in FeFETs.     

Off-state gate current with quasi-zero temperature coefficient in n-MOSFETs with reoxidized nitrided oxide as gate dielectric

Temperature stability of off-state gate current (I_g) for n-MOSFET's with reoxidized nitrided oxide (RNO) as gate dielectrics prepared by rapid thermal processing is investigated. A significant phenomeon that I_g remains almost unchanged at elevated temperature is observed. This could be attributed to the fact that reoxidation recovers part of the nitridation-induced lowering of barrier height for hole emission at the RNO/Si interface, resulting in the increases of the hot-hole injection which nearly compensate the decrease of hole generation at elevated temperature in the avalanche regime. The finding reveals a useful behavior with temperature-insensitive off-state gate current for RNO devices requiring a thermally stable operation.     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

On the InGaP/InxGa1−xAs pseudomorphic high electron-mobility transistors for high-temperature operations

The high-temperature characteristics of a novel InGaP/In_xGa_1−xAs pseudomorphic transistor with an inverted delta-doped channel are reported. Due to the presented wide-gap InGaP Schottky layer and the V-shaped In_xGa_1−xAs channel structure, the degradation of device performance with increasing the temperature is not so significant. Experimentally, for a 1×100 μm² device, the gate–drain voltages at a gate leakage current of 260 μA/mm and the maximum transconductances g_m,max are 30 (22.2) V and 201 (169) mS/mm at the temperature of 300 (450) K, respectively. Meanwhile, broad and flat drain current operation regimes for g_m, f_T and f_max are obtained.     

dc-Conduction mechanism in lanthanum–manganese oxide films grown on p-Si substrate

Thin films of (La–Mn) double oxide were prepared on p-Si substrates for electrical investigations. The samples have been characterised by X-ray fluorescence (XRF) and X-ray diffraction (XRD) methods. The XRF spectrum was used to determine the weight fraction ratio of Mn to La in the prepared samples. The XRD study shows the formation of grains of LaMnO₃ compound through a solid-state reaction for annealing at 800 °C. Samples used to study the electrical characteristics of the prepared films were constructed in form of a metal–oxide–Si MOS structures. Those MOS structures were characterised by the measuring their capacitance as a function of gate voltage C(V_g) in order to determine the oxide charge density Q_ox, the surface density of states D_it at the oxide/Si interface, and to extract the oxide voltage in terms of gate voltage. The extracted dielectric constant of the double oxide film is lower than that of pure La₂O₃ film and larger than that of pure Mn₂O₃ film, but the formation of LaMnO₃ grains by a solid-state reaction at 800 °C increases the relative permittivity to 11.5. These experimental conclusions might be useful to be used in the field of Si-oxide alternative technique. The leakage dc current density vs. oxide field J(E_ox) relationship for crystalline films follow the mechanism of Richardson–Schottky (RS), from which the field-lowering coefficient and the dynamic relative permittivity were determined. Nevertheless, the leakage current density measured in a temperature range of (293–363 K) was not controlled by the RS mechanism. It was observed that the temperature dependence of the leakage current in crystalline (La–Mn) oxide insulating films has metallic-like temperature behaviour, which might be important in the technical applications.     

A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under Vg=Vd

Hot-carrier degradation of n-MOSFETs at high gate voltages (V_g=V_d) is examined. A new lifetime prediction method is developed based on the universal power law between the degradation of saturated drain current (dI_dsat) and the product of the injected charge fluence times the gate current, which is independent of gate or drain voltages. This method is applied to 4 and 5 nm n-MOSFETs and lifetimes are estimated under their operation conditions. It is applicable to n-MOSFETs with ultrathin gate oxides.     

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF₂-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (V_th) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μ_eff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (J_g) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μ_eff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the J_g and robustness against reverse-bias stressing.     

Visible light emission from silicon MOSFETS

We observe visible light emission from Si MOSFET beyond source-drain breakdown. The intensity as well as location varies with gate bias. For zero gate-voltage (V_g) light is seen from four sides of the drain region. But for positive V_g values the location of the light emission shifts to the drain-gate boundary and has a peak in emission intensity at a certain gate bias beyond which it decreases. The initial increase in light intensity is attributed to minority-carrier injection and the decrease at higher gate bias is due to a reduction of lateral field beyond pinch off, which causes a decrease in carrier multiplication. For negative gate-bias, the source-drain breakdown voltage decreases and hence the light intensity increases. A theoretical model for the drain current beyond breakdown is presented and compared with experimental light-intensity curves. The substrate current, which is a measure of the avalanche mechanism by an electron-hole pair generation in the drain depletion region, is measured and compared with light-intensity values.     

高压LDMOS导通电阻的高温特性分析

本文提出了高压LDMOS的高温等效电路,讨论了LDMOS泄漏电流及本征参数在25℃~300℃范围内随温度变化规律.根据本文分析:源漏pn结的反向泄漏电流决定了LDMOS的高温极限温度;导通电阻与温度的关系是(T/T₁)^y(y为1.5~2.5).     

Edge inversion channels and surface leakage currents in high-voltage semiconductor devices

It is shown that the electric field over the surface of semiconductor devices can be sufficient to induce edge inversion channels if the bias voltage is high and the surface charge density Q _s is low. In this case, the edge region of the devices containing the p-n-p structure (e.g., that of thyristors) functions as a planar p-channel MIS transistor with a combined gate and drain and the entire medium over the surface functions as the gate insulator. The current between the source and drain of this “edge MIS transistor” is the surface leakage current of the entire device. An analytical theory describing the current-voltage characteristic in the subthreshold mode is developed. It is shown that this new mechanism controls the total leakage current of high-voltage devices if |Q _s | and temperature T are small enough (|Q _s | < 4 nC/cm², T < 270 K and |Q _s | < 58 nC/cm², T < 600 K for silicon and silicon carbide devices, respectively).     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

In0.48Ga0.52P/In0.20Ga0.80As/GaAs pseudomorphic high electron mobility transistors grown by solid-source molecular-beam epitaxy using a valved phosphorus cracker cell

In_0.48Ga_0.52P/In_0.20Ga_0.80As/GaAs pseudomorphic high electron mobility transistor (p-HEMT) structures were grown by solid-source molecular beam epitaxy (SSMBE) using a valved phosphorus cracker cell. The sheet carrier density at room temperature was 3.3 × 10¹²cm^?2. A peak transconductance (G _m) of 267 mS mm^?1 and peak drain current density (I _ds) of 360 mA mm^?1 were measured for a p-HEMT device with 1.25 µm gate length. A high gate-drain breakdown voltage (BV _gd) of 33V was measured. This value is more than doubled compared with that of a conventional Al_0.30Ga_0.70As/In_0.20Ga_0.80As/GaAs device. The drain-source breakdown voltage (BV _ds) was 12.5V. Devices with a mushroom gate of 0.25 µm gate length and 80 µm gate width achieved a peak transconductance (G _m) of 420 mS mm^?1 and drain current density of nearly 500mA mm^?1. A high cutoff frequency (f _T) of 58GHz and maximum oscillation frequency (f _max) of 120 GHz were obtained. The results showed that the In_0.48Ga_0.52P/In_0.20Ga_0.80As/GaAs material system grown by SSMBE using the valved phosphorus cracker cell for the In^0.48Ga^0.52P Schottky and spacer layers is a viable technology for high frequency p-HEMT device applications.     

Polymeric gate dielectric interlayer of cross-linkable poly(styrene-r-methylmethacrylate) copolymer for ferroelectric PVDF-TrFE field effect transistor memory

A new polymeric gate dielectric interlayer of a cross-linkable poly(styrene-random-methylmethacrylate) copolymer is introduced with a good thermal and chemical resistance in bottom gate Ferroelectric Field Effect Transistor (FeFET) memory with pentacene active layer and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) one. A thin uniform PVDF-TrFE film was successfully formed with well defined ferroelectric microdomains on an interlayer. Thickness of the interlayer turns out to be one of the most important factors for controlling gate leakage current which is supposed to be minimized for high ON/OFF bistability of a FeFET memory. An interlayer inserted between gate electrode and PVDF-TrFE layer significantly reduces gate leakage current, leading to source–drain OFF current of approximately 10^?11 A in particular when its thickness becomes greater than approximately 25 nm. A reliable FeFET device shows a clockwise I-V hysteresis with drain current bistablility of 10³ at ±40 V gate voltage.     

Sub-Band Filling and Hole Transport in Polythiophene-Based Electrolyte-Gated Transistors: Effect of Side-Chain Length and Density

The relationship between hole density and conductivity in electrochemically gated polythiophene films is examined. The films are  integrated into electrolyte-gated transistors (EGTs), so that hole accumulations can be electrochemically modulated up to ≈0.4 holes per thiophene ring (hpr). Polythiophenes include poly(3-alkylthiophenes) (P3ATs) with four different side chain lengths – butyl (P3BT), hexyl (P3HT), octyl (P3OT), or decyl (P3DT) – and poly[2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene] (PBTTT) and poly(3,3′′′-didodecyl[2,2′:5′,2′′:5′′,2′′′-quaterthiophene]-5,5′′′-diyl) (PQT). Analysis of the drain current – gate voltage (I_D–V_G) and gate current – gate voltage (I_G–V_G) characteristics of the EGTs reveals that all six polythiophene semiconductors exhibited reversible conductivity peaks at 0.12 – 0.15 hpr. Conductivity is suppressed beyond ≈0.4 hpr.The maximum carrier mobilities of the P3AT semiconductors increase, and hysteresis of the conductivity peaks decreases, with increasing alkyl side-chain length. PBTTT and PQT with reduced side chain densities exhibit the largest hysteresis but have higher hole mobilities. The results suggest that at ≈0.4 hpr, a polaronic sub-band is filled in all cases. Filling of the sub-band correlates with a collapse in the hole mobility. The side-chain dependence of the peak conductivity and hysteresis further suggests that Coulombic ion-carrier interactions are important in these systems. Tailoring ion-carrier correlations is likely important for further improvements in transport properties of electrochemically doped polythiophenes.     

Investigation of the Interfaces in Ni-FUSI/Hf-Based/Si and Ni-FUSI/SiO<Subscript>2</Subscript>/Si Stacks by Physical and Electrical Characterization Techniques

The combination of full Ni silicidation (Ni-FUSI) gate electrodes and hafnium-based high-k gate dielectrics is one of the most promising replacements for poly-Si/SiO₂/Si gate stacks for the future complementary metal–oxide–semiconductor (CMOS) sub-45-nm technology node. The key challenges to successfully adopting the Ni-FUSI/high-k dielectric/Si gate stack for advanced CMOS technology are mostly due to the interfacial properties. The origins of the electrical and physical characteristics of the Ni-FUSI/dielectric oxide interface and dielectric oxide/bulk interface were studied in detail. We found that Ni-FUSI undergoes a phase transformation during silicide formation, which depends more on annealing temperature than on the underlying gate dielectric material. The correlations of Ni–Si phase transformations with their electrical and physical changes were established by sheet resistance measurements, x-ray diffraction (XRD), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) analyses. The leakage current density–voltage (J–V) and capacitance–voltage (C–V) measurement techniques were employed to study the dielectric oxide/Si interface. The effects of the postdeposition annealing (PDA) treatment on the interface charges of dielectric oxides were studied. We found that the PDA can effectively reduce the trapping density and leakage current and eliminate hysteresis in the C–V curves. In addition, the changes in chemical bonding features at HfO₂/Si and HfSiO/Si interfaces due to PDA treatment were evaluated by XPS measurements. XPS analysis provides a better interpretation of the electrical outcomes. As a result, HfSiO films exhibited superior performance in terms of thermal stability and electrical characteristics.     

Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation

Degradation of the electrical performance in partially depleted SOI MOSFETs by 2-MeV electrons is presented. The degradation behavior of the 2^nd transconductance (g_mf) peak and its dependence on the back gate voltage is discussed taking into account the degradation of the back gate. The drain current in the subthreshold region is increased by irradiation. This is caused by the turn-on of the parasitic edge transistor. The 2^nd peak in the transconductance (g_mf) tends to decrease after irradiation, while less degradation is observed in the 1^st g_mf peak. The decrease of the 2^nd g_mf peak enhances by the application of a negative V_BG and the result can be explained by the degradation of the Si/buried oxide interface and the increase of the sidewall leakage, which gives rise to a lowering of the body potential.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

Deformation mechanism and its effect on electrical conductivity of ACF flip chip package under thermal cycling condition: An experimental study

In this study, experimental works are performed to investigate the deformation mechanism and electrical reliability of the anisotropic conductive adhesive film (ACF) joint subjected to temperature cycling for flip chip on organic board (FCOB) assemblies. This paper presents some dominant deformation parameters governing the electrical degradation in an ACF joint between a chip and a substrate when flip chip assembly is heated and cooled. The deformation mechanism of ACF flip chip assemblies during the temperature cycling are investigated using in situ high sensitivity moiré interferometry. A four-point probe method is conducted to measure the real-time contact resistance of ACF joint subjected to the cyclic temperature variation. As the temperature increases below T_g of ACF, the bending displacement of assembly decreases linearly. At the temperature higher than T_g of ACF, there is no further change in bending behavior and in-plane deformations of a chip and a substrate become approximately free thermal expansion. It is because that soft-rubbery ACF at the temperature above T_g cannot provide the mechanical coupling between a chip and a substrate. The effect of bump location on the temperature dependent contact resistance is evident. A characteristic hysteresis in bending curves is observed and discussed. The contact resistance of the corner bumps increases with increasing temperature at a higher rate when compared to that of the middle. Failure analysis is performed to examine the ACF interconnections before and after thermal cycling test. The results indicate that during the thermal loading, the shear deformation is more detrimental to the electrical degradation of ACF joints than normal strain.     

The forward bias current density–voltage–temperature (J–V–T) characteristics of Al–SiO2–pSi (MIS) Schottky diodes

Metal–insulator–semiconductor Schottky diodes were fabricated to investigate the tunnel effect and the dominant carrier transport mechanism by using current density–voltage (J–V) and capacitance–voltage (C–V) measurements in the temperature range of 295–370?K. The slope of the ln?J–V curves was almost constant value over the nearly four decades of current and the forward bias current density J is found to be proportional to J_o (T) exp(AV). The values of N_ss estimated from J–V and C–V measurements decreased with increasing temperature. The temperature dependence of the barrier heights obtained from forward bias J–V was found to be entirely different than that from the reverse bias C–V characteristics. All these behaviours confirmed that the prepared samples have a tunnel effect and the current transport mechanism in the temperature range of 295–370?K was predominated by a trap-assisted multi-step tunnelling, although the Si wafer has low doping concentration and the measurements were made at moderate temperature.