基于多种添加剂的TSV镀铜工艺研究

穿透硅通孔技术(TSV)是3D集成电路中芯片实现互连的一种新的技术解决方案,是半导体集成电路产业迈向3D封装时代的关键技术。在TSV制作主要工艺流程中,电镀铜填充是其中重要的一环。基于COMSOL Multiphysics平台,建立了考虑加速剂和抑制剂作用的硅通孔电镀铜仿真模型,仿真研究得到了基于硫酸铜工艺的最优电镀药水配方,并实验验证了该配方的准确性。     

后摩尔时代的封装技术

介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。     

3DIC集成与硅通孔（TSV）互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

硅通孔(TSV)转接板微组装技术研究进展

以硅通孔(TSV)为核心的三维集成技术是半导体工业界近几年的研发热点,特别是2.5D TSV转接板技术的出现,为实现低成本小尺寸芯片系统封装替代高成本系统芯片(So C)提供了解决方案。转接板作为中介层,实现芯片和芯片、芯片与基板之间的三维互连,降低了系统芯片制作成本和功耗。在基于TSV转接板的三维封装结构中,新型封装结构及封装材料的引入,大尺寸、高功率芯片和小尺寸、细节距微凸点的应用,都为转接板的微组装工艺及其可靠性带来了巨大挑战。综述了TSV转接板微组装的研究现状,及在转接板翘曲、芯片与转接板的精确对准、微组装相关材料、工艺选择等方面面临的关键问题和研究进展。     

3D堆叠技术及TSV技术

介绍了3D堆叠技术及其发展现状,探讨了W2W(Wafer to wafer)及D2W(Die to wafer)等3D堆叠方案的优缺点,并重点讨论了垂直互连的穿透硅通孔TSV(Through silicon via)互连工艺的关键技术,探讨了先通孔、中通孔及后通孔的工艺流程及特点,介绍了TSV的市场前景和发展路线图。3D堆叠技术及TSV技术已经成为微电子领域研究的热点,是微电子技术及MEMS技术未来发展的必然趋势,也是实现混合集成微系统的关键技术之一。     

硅通孔技术的发展与挑战

3D堆叠技术近年来发展迅速,采用硅通孔技术(TSV)是3D堆叠封装的主要趋势.介绍了3D堆叠集成电路、硅通孔互连技术的研究现状、TSV模型;同时阐述了TSV的关键技术与材料,比如工艺流程、通孔制作、通孔填充材料、键合技术等;最后分析了其可靠性以及面临的挑战.TSV技术已经成为微电子领域的热点,也是未来发展的必然趋势,运用它将会使电子产品获得高性能、低成本、低功耗和多功能性.     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

带有TSV的硅基大功率LED封装技术研究

介绍了一种带有凹槽和硅通孔(through silicon via,TSV)的硅基制备以及晶圆级白光LED的封装方法。针对硅基大功率LED的封装结构建立了热传导模型,并通过有限元软件模拟分析了这种封装形式的散热效果。模拟结果显示,硅基封装满足LED芯片p-n结的温度要求。实验结合半导体制造工艺,在硅基板上完成了凹槽和通孔的制造,实现了LED芯片的有效封装。热阻测试仪测得硅基的热阻为1.068K/W。实验结果证明,这种方法有效实现了低热阻、低成本、高密度的LED芯片封装,是大功率LED封装发展的重要方向。     

一种金属填充硅通孔工艺的研究

硅通孔(Through silicon via)的互连技术是3D IC集成中的一种重要工艺。报道了一种高深宽比的垂直互连穿透硅通孔工艺,其通孔的深宽比达到50以上;研究了利用钨填充硅通孔的一些关键工艺,包括阻挡层淀积工艺和钨填充工艺,分析了不同填充工艺所造成的应力的变化。最后获得了一种深宽比达到58∶1的深硅通孔无缝填充。     

硅通孔互连技术的开发与应用

随着三维叠层封装、MEMS封装、垂直集成传感器阵列以及台面MOS功率器件倒装焊技术的开发,硅通孔互连技术正在受到越来越广泛的重视和研究。文中叙述了几种硅通孔互连技术的制造方法,以及它们在三维封装、MEMS封装、高密度硅基板、垂直集成传感器阵列和台面MOS功率器件等方面的应用。最后,进一步阐述了硅通孔互连中几项关键技术的研究现状以及存在的挑战。     

三维集成技术的现状和发展趋势

给出了三维技术的定义,并给众多的三维技术一个明确的分类,包括三维封装(3D-P)、三维晶圆级封装(3DWLP)、三维片上系统(3D-SoC)、三维堆叠芯片(3D-SIC)、三维芯片(3D-IC)。分析了比较有应用前景的两种技术,即三维片上系统和三维堆叠芯片和它们的TSV技术蓝图。给出了三维集成电路存在的一些问题,包括技术问题、测试问题、散热问题、互连线问题和CAD工具问题,并指出了未来的研究方向。     

FOW在叠层CSP封装中的应用

随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的主要发展方向,叠层CSP封装具有封装密度高、互连性能好等特性,是实现三维封装的重要技术。针对超薄芯片传统叠层CSP封装过程中容易产生圆片翘曲、金线键合过程中容易出现0BOP不良、以及线孤（wireloop）的CPK值达不到工艺要求等问题,文中简要介绍了芯片减薄方法对圆片翘曲的影响,利用有限元（FEA）的方法进行芯片减薄后对悬空功能芯片金线键合（Wirebond）的影响进行分析,Filmon Wire（FOW）的贴片（DieAttach）方法在解决悬空功能芯片金线键合中的应用,以及FOW贴片方式对叠层CSP封装流程的简化。采用FOW贴片技术可以达到30％的成本节约,具有很好的经济效益。     

基于MCM-D工艺的3D-MCM工艺技术研究

基于MCM-D薄膜工艺,开展了3D-MCM相关的无源元件内埋置、芯片减薄、芯片叠层组装、低弧度金丝键合、芯片凸点,以及板级叠层互连装配等工艺技术研究。通过埋置型基板、叠层芯片组装、板级叠层互连,实现了3D-MCM结构,制作出薄膜3D-MCM样品;探索出主要的工艺流程及关键工序控制方法,实现了薄膜3D-MCM封装。     

MOSFET器件引线键合技术

MOSFET器件由于高阻抗、低功耗等特点,在电脑电源、家用电器和自动控制系统等方面得到广泛应用。但由于其芯片结构的特殊性,在封装制造过程中容易受到静电、应力、环境条件等多种因素的影响。引线键合过程是影响封装成品率的关键工艺环节。引线键合是电子工程互连的重要方式,MOSFET器件通常采用超声键合的工艺进行引线互连。影响引线键合质量的因素较多,其中引线键合工艺、引线材料和设备维护是最重要的三个因素。通过实际生产过程的试验、分析和提炼,研究引线键合技术,总结了引线键合工艺、引线材料和设备维护三个方面的实践经验,为提升和稳定封装成品率提供参考。     

A 54000-gate ECL array with substrate power supply

A sub-100-ps, 54000-gate ECL array with substrate power supply has been developed on a 64-mm/sup 2/ die. Gate density of 1160 gate/mm/sup 2/ is achieved by the newly developed 'CUBE' (Chip with Upside and Backside Electrodes) technology which enables a five-layer interconnection structure including heavily doped substrate and a polycide layer in addition to the conventional three metal layers. Gate delay of 96 ps with 2.4-mW power dissipation is obtained using double-polysilicon self-aligned transistor technology. The features of this technology are (1) high-density LSI resulting in improved interconnection delay and smaller chip size, (2) small voltage drops of power supply on the chip, and (3) an increased number of signal pads by eliminating V/sub EE/ pads from the top side of the chip.<>     

Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films

Much research has been carried out to realize through-silicon via (TSV) technology for three-dimensional (3D) chip stacking packaging. A vertical chip interconnection method using Cu/Sn-Ag bumps and nonconductive films (NCFs) is one of the most promising approaches for 3D TSV vertical interconnection. In this work, the relationship between the viscosity of pre-applied NCFs and loading forces was investigated to predict the gap change between a TSV chip and a substrate chip. Existing theories of squeeze flow are adapted to predict the gap change of a real TSV chip and a substrate chip during TSV bonding using a simplified model. The real gaps measured during bonding of test dies were matched to check the validity of the prediction model. Considering the thixotropy of NCFs, the prediction well matched the real gap changes between bumped TSV chips and substrate chips during bonding.     

Assembly of Copper Column Interconnect Flip Chip

This paper addresses a new flip chip interconnection technology, flexible flip chip connection (F2C2) technology, for attaching silicon chips to a chip carrier using flexible copper wires. F2C2 is a novel approach to create area array flip chip interconnections using a matrix block of wires encapsulated with a heat-resistant, dissolvable substance. A slice from the wire matrix ingot is first attached to the chip using solder. The other end of the slice is then matched and soldered to the footprint of a substrate. Finally, the encapsulating, dissolvable substance is removed from the body of the slice, leaving the chip attached to the carrier by the inter- disposed, flexible copper wires. The compliant copper wire interconnections can accommodate the coefficient of thermal expansion (CTE) mismatch problem between die and substrate, thus eliminating the need for underfill.     

A high-speed 16-kb GaAs SRAM of less than 5 ns using triple-levelmetal interconnection

The authors have realized 16-kb SRAMs with maximum address access time of less than 5 ns and typical power dissipation of less than 2 W at temperatures ranging from 25°C to 100°C. For the RAMs, they have developed a triple-level Au-based interconnection technology that reduces the wiring length and chip size of the SRAM so as to achieve high speed and high yield. Consequently, the wiring length and chip size are reduced to 69% and 58%, respectively, of those obtained by in previous work. The authors experimentally compared the delay time incurred by double-level interconnection and that by triple-level interconnection. This ratio is found to agree well with the simulated one by a model with distributed RC delay. After successfully suppressing Au hillock generation by lowering the process temperature, yield per wafer of 10% is obtained     

Highly Conductive,Flexible, Polyurethane‐Based Adhesives for Flexible and Printed Electronics

Flexible interconnects are one of the key elements in realizing next‐generation flexible electronics. While wire bonding interconnection materials are being deployed and discussed widely, adhesives to support flip‐chip and surface‐mount interconnections are less commonly used and reported. A polyurethane (PU)‐based electrically conductive adhesive (ECA) is developed to meet all the requirements of flexible interconnects, including an ultralow bulk resistivity of ≈1.0 × 10^?5 Ω cm that is maintained during bending, rolling, and compressing, good adhesion to various flexible substrates, and facile processing. The PU‐ECA enables various interconnection techniques in flexible and printed electronics: it can serve as a die‐attach material for flip‐chip, as vertical interconnect access (VIA)‐filling and polymer bump materials for 3D integration, and as a conductive paste for wearable radio‐frequency devices.     

基于光电混合集成的四通道外调电/光转换组件

由于单片级集成技术面临开发成本高、周期长等问题,提出一种基于光电混合集成封装的四通道外调电/光转换组件。该组件利用光电混合集成技术,采用空间光学透镜耦合代替原有光纤互连方式、传输微带代替传统电缆互连方式、金丝/金带代替传统低频导线方式以及微组装工艺实现多专业裸芯片一体化气密封装代替分离组件混合装配方式,从而达到大幅度压缩体积、提高集成度的目的。测试结果表明:该组件实现了四通道2~18 GHz的电/光转换功能,波长序列满足8个信道200 GHz通道间隔要求,射频指标S21值为-4 dB±3 dB,驻波小于1.5,噪声系数小于23 dB。