共查询到18条相似文献,搜索用时 93 毫秒
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研究了JPEG2000压缩标准及单片实现该标准的专用编解码芯片ADV212,并在分析ADV212的硬件结构及工作原理的基础上,设计了一种ADV212组合Field Programmable Gate Array(FPGA)的静态图像数据压缩电路.其中,系统数据接口采用Universal Serial Bus(USB),FPGA用来实现时序控制和输入输出数据格式的组织,ADV212则进行小波分解和码流组织,以完成图像数据的压缩.利用该系统对标准静态图像的压缩试验表明,系统工作正确可靠,可用于实际图像压缩. 相似文献
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基于ADV212的远程图像采集系统设计 总被引:1,自引:0,他引:1
针对彩色高清图像远程网络传输带宽需求过大的问题,提出了基于ADV212图像压缩芯片结合FP-GA的压缩、传输解决方案。设计中以彩色高清Bayer格式CMOS作为图像传感器,使用ADV212实现对图像的快速高质量压缩,通过FPGA实现整个系统的控制逻辑,实现对ADV212的配置、驱动以及压缩前图像的分配和压缩后码流数据的打包处理。实验表明该系统可以保证接收图像具有较高的峰值信噪比,能够长期稳定地工作在36Mbyte/s的图像输入条件下,且该系统具有体积小、使用灵活方便、带宽占用低和压缩率可调等优点。 相似文献
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多光谱可见光遥感图像压缩系统设计 总被引:2,自引:0,他引:2
为了实现多光谱可见光遥感图像高质量压缩的要求,提出以JPEG2000压缩标准为理论,将FPGA与专用压缩芯片ADV212相结合的空间遥感图像压缩方法.该系统设计采用ADV212,通过小波变换及熵编码实现对大数据量的空间遥感图像进行高质量实时压缩,并且采用FPGA完成图像数据输入、压缩码流输出、图像预处理以及对ADV212的工作模式进行控制.实验结果表明,该系统设计功耗低、成本低、调试简单合理,具有较好的压缩效果,可满足多光谱可见光遥感图像对高质量压缩比的要求. 相似文献
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介绍了居于小波视频编解码芯片ADV612的远程图像采集器实现,解决了视频数据压缩问题,实现了视频数据采集器的小型化、智能化。 相似文献
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由于空间遥测图像的数据量大,通信带宽有限,所以对遥测图像进行压缩编码,节省传输时占用带宽资源和减少数据存储量,才能将遥测信号更可靠、全面地进行传输或是存储到记录器中留待分析使用。综合遥测系统在传输图像时要在尽量小的空间中最大化地采集和传输图像信息的特殊要求,设计采用FPGA+专用视频解码芯片ADV7180来实现视频图像采集模块的功能,采用FPGA+专用图像压缩芯片ADV212来完成视频图像压缩功能的设计。最终实现了压缩率约为25倍,压缩后的数据传输速率达到40 Mbit/s的视频图像采集压缩系统。该系统具有体积小、成本低、可靠性高、开发周期短等优点。 相似文献
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基于ADV212的光谱数据压缩系统研究 总被引:1,自引:0,他引:1
为了解决现有的存储介质和传输带宽与成像光谱仪(imaging spectrometer)异常庞大的光谱数据量之间的矛盾,本论文选用FPGA搭载JPEG2000压缩专用图像压缩芯片ADV212的方式;利用Xilinx的嵌入式开发套件所提供的可编程嵌入式开发平台和Xilinx MicroBlaze软核处理器设计了硬件系统来实现光谱数据压缩。系统设计使用专用图像压缩芯片,所以不必花费大量时间对JPEG2000算法进行优化,处理数据的速度较高,还原图像的质量较好而且实现起来简单,技术成熟可靠稳定。并在基于DMD的哈达玛成像光谱仪上对所设计系统进行了验证。结果表明该系统达到实时压缩光谱数据的要求。 相似文献
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针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。 相似文献
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Michalis D. Galanis Athanassios Milidonis Athanassios P. Kakarountas Costas E. Goutis 《Microelectronics Journal》2006,37(6):554-564
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications. 相似文献
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Alexandros Vavousis Andreas Apostolakis Mihalis Psarakis 《Journal of Electronic Testing》2013,29(6):805-823
The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor. 相似文献
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针对传统工业图像实时压缩采集系统中图像数据传输较慢、信号干扰大、压缩不稳定等问题,提出了一种优化设计方案。该设计以FPGA为主控单元,采用标准压缩芯片ADV212进行图像实时压缩处理,并对LVDS传输图像数据的方法进行优化,由传统的外部串化芯片MAX9247和解码芯片MAX9250改为FPGA内部原语OSERDES2和ISERDES2实现数据的串化和解串。实验结果表明,并行数据的传输速率由原来的35MHz提升到50MHz,大幅提升了数据传输的速率,在同样的压缩倍数下,得到了更为清晰稳定的压缩图像。 相似文献
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介绍了一种高分辨率图像采集卡的系统实现,该系统主要由AD9884A,FPGA,SDRAM,PCI总线控制器等构成,其中由FPGA实现器件的接口控制电路和图像数据压缩等功能,在FPGA的控制下,图像经采集压缩处理后通过PCI总线传送给PC机,达到实时存储的目的. 相似文献