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1.
介绍了一个工作于快照模式的CMOS焦平面读出电路的低功耗新结构-OESCA(Odd-Even SnapshotCharge Amplifier)结构该结构像素电路非常简单,仅用三个NMOS管;采用两个低功耗设计的电荷放大器做列读出电路,分别用于奇偶行的读出,不但可有效消除列线寄生电容的影响,而且列读出电路的功耗可降低1 5%,因此OESCA新结构特别适于要求低功耗设计的大规模、小像素阵列焦平面读出电路采用OESCA结构和1.2μm双硅双铝标准CMOS工艺设计了一个64×64规模焦平面读出电路实验芯片,其像素尺寸为50μm×50μm,读出电路的电荷处理能力达10.37pC.详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的SPICE仿真结果和试验芯片的测试结果.  相似文献   

2.
介绍了一个工作于快照模式的 CMOS焦平面读出电路的低功耗新结构— OESCA (Odd- Even SnapshotCharge Am plifier)结构 .该结构像素电路非常简单 ,仅用三个 NMOS管 ;采用两个低功耗设计的电荷放大器做列读出电路 ,分别用于奇偶行的读出 ,不但可有效消除列线寄生电容的影响 ,而且列读出电路的功耗可降低 15 % ,因此 OESCA新结构特别适于要求低功耗设计的大规模、小像素阵列焦平面读出电路 .采用 OESCA结构和 1.2μm双硅双铝标准 CMOS工艺设计了一个 6 4× 6 4规模焦平面读出电路实验芯片 ,其像素尺寸为 5 0μm× 5 0μm ,读出电路的电荷处理能力达 10 .3  相似文献   

3.
徐斌  袁永刚  李向阳 《半导体光电》2014,35(5):768-772,806
为提高紫外焦平面组件成像质量,提出了可用于紫外焦平面的像素级数字化读出电路结构。针对紫外信号微弱及焦平面探测器像素面积小的特点,设计了基于电容反馈跨阻放大器(Capacitive Trans-Impedance Amplifier,CTIA)结构、模数转换器和锁存器的紫外焦平面像素级模数转换读出电路,并给出了实现像素内模数转换的工作原理。详细讨论了像素内模数转换的实现方法,各模块的设计要求及其具体实现,并基于0.35μm DP4M CMOS工艺设计制造了面阵规模128×128、像素单元面积50μm×50μm的读出电路芯片。电路性能测试与成像实验表明:电路的精度达到1mV以下,有效位数达到11位,实现了紫外焦平面读出电路的低噪声数字化输出。  相似文献   

4.
刘震宇  赵建忠 《激光与红外》2008,38(10):1042-1045
针对一款大面阵(640×512元)快照模式制冷型红外焦平面用的读出电路进行了初步分析验证.该读出电路采用改进DI结构,先积分后读出的积分控制模式,像素尺寸为25μm×25μm,芯片已在0.5μm双硅双铝(DPDM)标准CMOS工艺下试制.首先对该电路结构及工作原理进行分析,并对输入级等电路的传输特性进行仿真验证,最后给出探测器阵列与读出电路芯片互连后的测试结果.结果表明该读出电路适用于小像素、大规模的红外焦平面阵列.  相似文献   

5.
文中介绍了一种新型的128×128红外读出电路中的低功耗设计,包括像素级和列读出级两部分.在像素级设计中,提出了一种新型四像素共用反馈放大器(Quad-Share Buffered Injection,QSBDI)的结构:每个像素的平均功耗为500nW,放大器引入的功耗降低了30%,同时使像素FPN只来源于局部失配.列读出级采用新型主从两级放大列读出结构,其中主放大器完成电荷到电压的转换,从放大器驱动输出总线来满足一定的读出速度.通过SPICE仿真发现,与传统列电荷放大器结构相比,新型结构可节省60%的功耗.  相似文献   

6.
128×128元氮化镓紫外焦平面读出电路的设计与封装研究   总被引:1,自引:0,他引:1  
随着GaN基紫外材料的成熟,GaN基紫外探测器迅速发展,半导体紫外探测技术成为继红外和激光探测技术后发展起来的又一新型光电探测技术.GaN基紫外探测器以其固有的量子效率高、可靠性高、使用方便等特点,将在紫外探测、预警、天际及地空通信和紫外弱光成像系统等领域发挥重要作用.读出电路作为紫外焦平面信号调理与输出部分对紫外焦平面组件性能起至关重要的作用.封装是通用传感器组件应用前的一道重要工序,合理的封装结构对组件及系统是必要的.描述了128×128元紫外焦平面读出电路与封装的设计过程,用Cadence与Hspice软件仿真分析了3×3元读出电路的工作点以及封装要考虑的热耗散问题,最后给出了读出电路的工作点与合理封装形式的建议.文中提到的128×128元50 μm×50μm紫外读出电路已设计完成并采用Charter线宽为0.35 μm的2P4MCMOS工艺流片.  相似文献   

7.
报道了128×128 AlGaAs/GaAs量子阱红外焦平面探测器阵列的设计和制作.采用金属有机化学气相淀积外延技术生长外延材料,并在GaAs集成电路工艺线上完成工艺制作.为得到器件参数,设计制作了台面尺寸为300μm×300μm的大面积测试器件;77K下2V偏压时暗电流密度为1.5×10-3A/cm2;80K工作温度下,器件峰值响应波长为8.4μm,截止波长为9μm,黑体探测率DB 为3.95×108(cm·Hz1/2)/W.将128×128元 AlGaAs/GaAs量子阱红外焦平面探测器阵列芯片与相关CMOS读出电路芯片倒装焊互连,在80K工作温度下实现了室温环境目标的红外热成像,盲元率小于1%.  相似文献   

8.
报道了128×128 AlGaAs/GaAs量子阱红外焦平面探测器阵列的设计和制作.采用金属有机化学气相淀积外延技术生长外延材料,并在GaAs集成电路工艺线上完成工艺制作.为得到器件参数,设计制作了台面尺寸为300μm×300μm的大面积测试器件;77K下2V偏压时暗电流密度为1.5×10-3A/cm2;80K工作温度下,器件峰值响应波长为8.4μm,截止波长为9μm,黑体探测率DB 为3.95×108(cm·Hz1/2)/W.将128×128元 AlGaAs/GaAs量子阱红外焦平面探测器阵列芯片与相关CMOS读出电路芯片倒装焊互连,在80K工作温度下实现了室温环境目标的红外热成像,盲元率小于1%.  相似文献   

9.
基于串行单斜率积分的原理,提出了一种新型的像素级红外焦平面片上8位模数转换电路.设计了一个8×8像素阵列组成的完整读出电路芯片,并进行了版图设计和电路仿真.每个单元像素电路采用直接注入方式输入,输出与输入电流成正比的数字脉冲信号,经每列单元共享的计数器计数输出.采用独特的数字电路列共享结构,电荷注入补偿等技术,具有结构简单、面积小等特点.仿真及测试结果表明,该芯片能较好地完成红外焦平面信号读出及模数转换功能,单元面积80 μm×80 μm,单元功耗50 μW,量化等级达到8位,芯片实测量化误差小于4 LSB,帧速可达460 f/s.  相似文献   

10.
介绍了一种面向384×288 CMOS面阵性红外读出电路的低功耗设计.针对探测器的特点(输出阻抗约100kΩ,积分电流约100nA),新提出并实现了一种四像素共用BDI的QSBDI(Quad-share BDI)像素结构.在QSBDI结构中,4个相邻的像素共用一个反馈放大器,从而实现了高注入效率、稳定的偏置、较好的FPN特性和低功耗.另外该384×288读出电路还支持积分然后读出、积分同时读出功能,还有两个可选择的增益以及4种窗口读出模式.128×128的测试读出电路已完成设计、加工和测试.电路使用CSMC0.5μm DPTM工艺流片,测试结果表明在每个子阵列输出的峰峰差异仅为10mV.在4MHz的工作频率下,像素级引入的功耗仅为1mW,芯片的整体功耗也只有37mW,实现了低功耗设计.  相似文献   

11.
提出了一种快闪式红外焦平面阵列读出电路。采用改进的直接注入型单元电路,积分电容大小可选,能适应大范围的光背景条件,并且增加了图像变换(倒置/反转)功能。一款128×128阵列的读出电路已经基于标准0.5μmCMOS工艺实现,整体芯片的面积为8.0mm×8.5mm。实测结果表明,此读出电路具有良好的光电转换能力,同时具有功耗低、输出摆幅大、动态范围大等优点。  相似文献   

12.
A new CMOS current readout structure for the infrared (IR) focal-plane-array (FPA), called the buffered gate modulation input (BGMI) circuit, is proposed in this paper. Using the technique of unbalanced current mirror, the new BGMI circuit can achieve high charge sensitivity with adaptive current gain control and good immunity from threshold-voltage variations. Moreover, the readout dynamic range can be significantly increased by using the threshold-voltage-independent current-mode background suppression technique. To further improve the readout performance, switch current integration techniques, shared-buffer biasing technique, and dynamic charging output stage with the correlated double sampling circuit are also incorporated into the BGMI circuit. An experimental 128×128 BGMI readout chip has been designed and fabricated in 0.8 μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip under 77 K and 5 V supply voltage have successfully verified both readout function and performance improvement. The fabricated chip has the maximum charge capacity of 9.5×107 electrons, the transimpedance of 2.5×109 Ω at 10 nA background current, and the arrive power dissipation of 40 mW. The uniformity of background suppression currents can be as high as 99%. Thus, high injection efficiency, high charge sensitivity, large dynamic range, large storage capacity, and low noise can be achieved In the BGMI circuit with the pixel size of 50×50 μm2. These advantageous characteristics make the BCMI circuit suitable for various IR FPA readout applications with a wide range of background currents  相似文献   

13.
A new CMOS readout circuit for VO2-based uncooled FPAs is presented in this paper. The on-chip readout circuit consists of three major parts: An input circuit of BCDI structure, a column-shared integration circuit of CTIA structure, and a common CDS output circuit. The simple configuration of the input circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels, the column-shared integration circuit which is suitable for small pixel size provides low noise, high gain, a highly stable detector bias, and high photon current injection efficiency, and the common CDS output circuit is utilized to reduce or eliminate low-frequency noise of the readout circuit. An experimental readout chip for 50-μm-pitch 32×32 element VO2-based uncooled FPAs has been fabricated. The measurement results of the fabricated readout chip have successfully verified its readout function and excellent performance.  相似文献   

14.
The design and measurement of a snap-shot mode cryogenic readout circuit (ROIC) for GaAs/AlGaAs QWIP FPAs was reported. CTIA input circuits with pixel level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array. Design optimization techniques for cryogenic and low power are analyzed. An experimental ROIC chip of a 128 × 128 array was fabricated in 0.35μm CMOS technology. Measure-ments showed that the ROIC could operate at 77 K with low power dissipation of 35 mW. The chip has a pixel charge capacity of 2.57 × 10~6 electrons and transimpedance of 1.4 × 10~7 Ω. Measurements showed that the transimpedance non-uniformity was less than 5% with a 10 MHz readout speed and a 3.3 V supply voltage.  相似文献   

15.
To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.  相似文献   

16.
设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。  相似文献   

17.
A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm2. Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×108 electrons, a maximum transimpedance of 1×109 Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's  相似文献   

18.
提出了一种基于6T像素结构的全局曝光CMOS图像传感器。通过采用PPD结构的6T像素、高复位电平和低阈值器件,提高了动态范围,并优化设计了像素单元的版图,使之获得较高的填充系数;模拟读出电路部分,通过采用双采样、增益放大和减小列级固定模式噪声(FPN)处理,以及对列选控制电路进行优化,减小了对全局PGA的运放设计要求。芯片的工作频率为20MHz,动态范围为66dB,实现了全局曝光方式CMOS图像传感器的设计。  相似文献   

19.
李琰  Yavuz De 《电子学报》2009,37(7):1393-1399
本文研究了一个采用标准0.35μm CMOS 工艺制造的新型高能物理粒子轨迹追踪器.这个新型的追踪器运用CMOS有源像素传感器技术(CMOS Monolithic Active Pixel Sensors,MAPS)将信号的探测与处理电路集成在一起,在像素的内部实现了相关双次采样操作(Correlated Doubled Sampling,CDS).实验芯片包含一个128行×32列的像素矩阵,其中,像素的大小为25×25μm2.通过采用放射源55Fe的测定, 得到像素的等效输入随机噪声 (Temporal Noise) 仅为12个电子而固定噪声(Fixed Pattern Noise,FPN)仅为4个电子.传感器的电荷-电压转换系数(Charge-to-Voltage conversion Factor,CVF)为60μV/e-.测试中,芯片的信号读取速度达到了12μs/帧.  相似文献   

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