一种BiCMOS高速、低压、低功耗全摆幅单元电路技术

提出了一种具有高速全摆幅输出的BiCMOS缓冲器逻辑单元.该单元可以工作于1.5V,并且易于实现多输入扩展.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路——complementary pass- transistor adiabatic logic (CPAL ) .电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MO-SIS的0 .2 5μm CMOS工艺,在5 0～2 0 0 MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2 N - 2 N2 P电路的5 0 %和35 % .     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

低位线摆幅的低功耗SRAM设计

本文提出了一种低位线摆幅（LVBS）的低功耗SRAM结构。这种SRAM采用电荷分享方法降低线电压幅值，在写操作时使得位线电压摆幅减少了50％，从而显著降低了位线动态功耗。同时本文还分析了由于位线电压降低带来的静态噪声容限（SNM）等问题。实验结果表明相比较常规SRAM，LVBS SRAM可以节约30％的动态功耗。     

时钟低摆幅双边沿低功耗触发器的设计

传统的时钟低摆幅触发器由于工作方式和电路结构不够合理,使得电路的结点电容和开关活动性较大,增加了电路的开关功耗.本文通过改进传统的时钟低摆幅触发器的工作方式和电路结构,设计了一种新型的时钟低摆幅双边沿触发器--反馈保持型时钟低摆幅双边沿触发器(Feedback Keeper Low-swing Clock Double-edge-triggered Flip-flop-FK-LSCDFF).模拟结果表明所设计的触发器具有正确的逻辑功能,跟传统的时钟低摆幅双边沿触发器相比,降低近17%的功耗.     

一种低电压全摆幅CMOS运算放大器

提出了一种工作于 3 V电压、输入输出均为全摆幅的两级 CMOS运算放大器。为使放大器有较小的静态功耗 ,运算放大器的输入级被偏置在弱反型区 ;输出级采用甲乙类共源输出级 ,以达到输出电压的全摆幅。模拟结果显示 ,在 1 0 kΩ负载下 ,运算放大器的直流开环增益为 81 d B,共模抑制比 91 d B;在 3 p F电容负载下 ,其单位增益带宽为 1 .8MHz,相位裕度 5 9°     

一个低功耗高摆幅电压模式发送端

本文设计完成了一个28纳米工艺下的低功耗电压模式发送端. 相比于电流模式发送端。电压模式发送端输出更大摆幅的信号的同时功耗更低。发送端通过电压转换器被分为两个电压域用于减小功耗。另外,本文提出的电压结构能够实现相互独立的阻抗匹配和均衡控制。 芯片实测发送端可输出差分摆幅880毫伏的信号,并且每个通道的功耗仅为23毫瓦。     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

全摆幅运算放大器的设计

设计了一种全摆幅输入的运算放大器。通过恒定跨导结构实现互补输入差分对共模输入电压在轨到轨范围内对恒定跨导的控制。设计中在输出结构里使用了电流求和电路,以达到输出信号相加,实现单端输出的功能。采用Spectre进行仿真,电源电压5V时,低频增益84dB,单位增益带宽12MHz。     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。     

一种高速低功耗MOS电流模逻辑加法器的设计

对具有不同输入端的MOS电流模逻辑(MCML)门电路进行了设计分析,应用MCML单元逻辑电路,设计了一个4位超前进位加法器.基于SMIC 0.13 μm CMOS工艺平台,对设计的加法器进行仿真.结果表明,该加法器的延迟比传统CMOS电路小,可广泛用于高速低功耗逻辑运算单元.     

面向低功耗的全加器优化设计

在对现有全加器电路研究分析的基础上，提出了基于传输管逻辑的低功耗全加器。电路采用对称结构，平衡了电路延迟，消除了毛刺，降低了功耗。经PSPICE在0．24μm工艺下模拟仿真，与已发表的全加器电路的性能进行比较。测试结果表明，改进的新全加器功耗可减小77．5％，同时能耗也是最低的。     

反转矢量透射反馈求解光电混合全加器

提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器，该加法器可以实现两输入的光学算术运算，研制成的各单元器件可用于其它各种光计算机系统中。     

一种基于互补型单电子晶体管的全加器电路设计

基于单电子晶体管(SET)的I-V特性和CMOS数字电路的设计思想,提出了一种由28个互补型SKT构成的全加器电路结构。该全加器优点为：简化了“P—SET”逻辑块;通过选取一组参数使输入和输出高低电平都接近于0．02mV和0mV,电压兼容性好;延迟时间短,仅为0．24ns。SPICE宏模型仿真结果验证了它的正确性。     

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

基于单电子晶体管的动态全加器电路设计

基于单电子晶体管的I-V特性,运用CMOS动态电路的设计思想,提出了一种基于单电子晶体管的全加器动态电路,利用SPICE对设计的电路进行了仿真验证,分析了电荷分享问题.相对于静态互补逻辑电路的设计方法,基于单电子晶体管的动态逻辑电路不仅克服了单电子晶体管固有的电压增益低的缺点,而且器件数目也大幅减少.多栅SET的使用可以减少电荷分享问题对动态电路的影响.     

An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

The design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.     

Design and analysis of a high-performance CNFET-based Full Adder

This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C _out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technologies. The simulation results demonstrate the superiority of the proposed design in terms of speed, power consumption, power delay product, and less susceptibility to process variations, compared to other classical and modern CMOS and CNFET-based Full Adder cells.