GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.     

Unpassivated AlGaN-GaN HEMTs with minimal RF dispersion grown by plasma-assisted MBE on semi-insulating 6H-SiC substrates

High electron mobility transistors (HEMTs) are fabricated from AlGaN-GaN heterostructures grown by plasma-assisted molecular beam epitaxy (MBE) on semi-insulating 6H-SiC substrates. At a sheet charge density of 1.3 /spl times/ 10/sup 13/ cm/sup -2/, we have repeatedly obtained electron mobilities in excess of 1350 cm/sup 2//Vs. HEMT devices with a gate length of 1/spl mu/m, a gate width of 200 /spl mu/m, and a source-drain spacing of 5 /spl mu/m show a maximum drain current of 1.1 A/mm and a peak transconductance of 125 mS/mm. For unpassivated HEMTs, we measured a saturated power output of 8.2-W/mm continuous wave (cw) at 2 GHz with an associated gain of 11.2 dB and a power-added efficiency of 41%. The achievement of high-power operation without a surface passivation layer suggests that free surface may not be the dominant source of radio-frequency (RF) dispersion in these MBE-grown structures. This data may help discriminate between possible physical mechanisms of RF dispersion in AlGaN-GaN HEMTs grown by different techniques.     

Variable numerical-aperture temporal-coherence measurement of resonant-cavity LEDs

The first interferometric measurements of temporal-coherence length variation with numerical aperture (NA) are described for 650 nm, resonant-cavity light-emitting diodes (LEDs) agreeing with spectrally derived results. The interferometrically measured coherence length (22 /spl mu/m to 32 /spl mu/m) reduced by 37% for a 0.42 increase in NA. For a larger range of NA (0-1), this would give coherence lengths (10 /spl mu/m-40 /spl mu/m) lying in the gap between that of conventional LEDs (/spl sim/5 /spl mu/m) and superluminescent diodes (/spl sim/60 /spl mu/m).     

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using new wiring technology, referred to as CLOSE Wiring, CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4% fill factor in a 30 /spl mu/m/spl times/30 /spl mu/m pixel, a 3.9 mm/spl times/3.9 mm image area, and a 5.5 mm/spl times/5.5 mm chip size. The charge handling capability for the 3.3 /spl mu/m wide VCCD achieves 9.8/spl times/10/sup 5/ electrons, The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with a 50 mm f/1.3 lens.<>     

A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

1.55-/spl mu/m InP-InGaAsP Fabry-Perot lasers with integrated spot size converters using antiresonant reflecting optical waveguides

We demonstrate a new concept for InGaAsP-InP 1.55-/spl mu/m Fabry-Perot lasers integrated with spot size converters using type-A antiresonant reflecting optical waveguides. The fabrication of such devices allows to avoid the growth of thick layers of quaternary material with low Ga and As fraction, which are difficult to achieve and grow. Reduced far-field divergence angles (10/spl deg/ /spl times/ 27/spl deg/) and improved coupling to cleaved standard single-mode fibers (2.6-dB coupling loss) are achieved. The proposed device is compatible with conventional epitaxial techniques and lithographic methods.     

Low threshold high-power room-temperature continuous-wave operation diode laser emitting at 2.26 /spl mu/m

Diode lasers emitting at 2.26 /spl mu/m, based on the InGaAsSb-AlGaAsSb materials system, are reported. These devices exhibit high internal quantum efficiency of 78% and low threshold current density of 184.5 A/cm/sup 2/ for a 2-mm-long cavity. Output power up to 700 mW (/spl ap/550 mW) has been obtained at 280 K (300 K) in continuous-wave operation with 100 /spl mu/m/spl times/1 mm lasers. These devices have been coated with an antireflection on the output facet and are mounted epilayer down on a copper block. The working temperature was maintained by a thermoelectric Peltier cooling element.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

Millimeter-wave high-power 0.25-/spl mu/m gate-length AlGaN/GaN HEMTs on SiC substrates

Reports on the CW power performance at 20 and 30 GHz of 0.25 /spl mu/m /spl times/ 100 /spl mu/m AlGaN/GaN high electron mobility transistors (HEMTs) grown by MOCVD on semi-insulating SiC substrates. The devices exhibited current density of 1300 mA/mm, peak dc extrinsic transconductance of 275 mS/mm, unity current gain cutoff (f/sub T/) of 65 GHz, and maximum frequency of oscillation (f/sub max/) of 110 GHz. Saturated output power at 20 GHz was 6.4 W/mm with 16% power added efficiency (PAE), and output power at 1-dB compression at 30 GHz was 4.0 W/mm with 20% PAE. This is the highest power reported for 0.25-/spl mu/m gate-length devices at 20 GHz, and the 30 GHz results represent the highest frequency power data published to date on GaN-based devices.     

Improvement of dark current using InP/InGaAsP transition layer in large-area InGaAs MSM photodetectors

A large-area InGaAs metal-semiconductor-metal (MSM) photodetector with 1/spl times/1 mm/sup 2/ photoactive area for free-space optical communication applications has been designed, fabricated, and characterized. Interdigitated electrodes of 2-/spl mu/m widths and 15-/spl mu/m spacings are designed to maximize the responsivity, and enable MSM photodetectors to reach a maximum responsivity at 1.53-/spl mu/m wavelength. By employing a two-step InP/InGaAsP transition layer, the dark current density of 45 fA//spl mu/m/sup 2/ was achieved at 10-V bias and at room temperature. Dark current-bias voltage curves were measured as a function of temperature from 40 to 270 K to estimate the activation energy. A 3-dB bandwidth of 210 MHz was obtained at a 10-V bias, and the measured result was compared with the designed bandwidth.     

Low-loss InGaAsP/InP submicron optical waveguides fabricated by ICP etching

The fabrication and characterisation of low-loss InGaAsP/InP optical submicron waveguides made with ICP etching is reported. Their width ranges from 0.2 to 2 /spl mu/m. For the 0.5 /spl mu/m width, the propagation losses at /spl lambda/=1.55 /spl mu/m as low as 4.2 dB/mm have been measured.     

AlGaN-GaN HEMTs on Si with power density performance of 1.9 W/mm at 10 GHz

AlGaN-GaN high electron mobility transistors (HEMTs) on silicon substrate are fabricated. The device with a gate length of 0.3-/spl mu/m and a total gate periphery of 300 /spl mu/m, exhibits a maximum drain current density of 925 mA/mm at V/sub GS/=0 V and V/sub DS/=5 V with an extrinsic transconductance (g/sub m/) of about 250 mS/mm. At 10 GHz, an output power density of 1.9 W/mm associated to a power-added efficiency of 18% and a linear gain of 16 dB are achieved at a drain bias of 30 V. To our knowledge, these power results represent the highest output power density ever reported at this frequency on GaN HEMT grown on silicon substrates.     

30-W/mm GaN HEMTs by field plate optimization

GaN high-electron-mobility-transistors (HEMTs) on SiC were fabricated with field plates of various dimensions for optimum performance. Great enhancement in radio frequency (RF) current-voltage swings was achieved with acceptable compromise in gain, through both reduction in the trapping effect and increase in breakdown voltages. When biased at 120 V, a continuous wave output power density of 32.2 W/mm and power-added efficiency (PAE) of 54.8% at 4 GHz were obtained using devices with dimensions of 0.55/spl times/246 /spl mu/m/sup 2/ and a field-plate length of 1.1 /spl mu/m. Devices with a shorter field plate of 0.9 /spl mu/m also generated 30.6 W/mm with 49.6% PAE at 8 GHz. Such ultrahigh power densities are a dramatic improvement over the 10-12 W/mm values attained by conventional gate GaN-based HEMTs.     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

30-GHz-band over 5-W power performance of short-channel AlGaN/GaN heterojunction FETs

This paper describes the small-signal characterization through delay-time analysis and high-power operation of the Ka-band of AlGaN/GaN heterojunction field-effect transistors (FETs). An FET with a gatewidth of 100 /spl mu/m and a gate length of 0.09 /spl mu/m has exhibited a current gain cutoff frequency (f/sub T/) of 81 GHz, a maximum frequency of oscillation (fmax) of 187 GHz, and a maximum stable gain of 10.5 dB at 30 GHz (8.3 dB at 60 GHz). Delay-time analysis has demonstrated channel electron velocities of 1.50/spl times/10/sup 7/ to 1.75/spl times/10/sup 7/ cm/s in a gate-length range of 0.09-0.25 /spl mu/m. State-of-the-art performance-saturated power of 5.8 W with a linear gain of 9.2 dB and a power-added efficiency of 43.2%-has been achieved at 30 GHz using a single chip having a gatewidth of 1.0 mm and a gate length of 0.25 /spl mu/m.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

High-performance double-recessed enhancement-mode metamorphic HEMTs on 4-in GaAs substrates

Enhancement-mode InAlAs/InGaAs/GaAs metamorphic HEMTs with a composite InGaAs channel and double-recessed 0.15-/spl mu/m gate length are presented. Epilayers with a room-temperature mobility of 10 000 cm/sup 2//V-s and a sheet charge of 3.5/spl times/10/sup 12/cm/sup -2/ are grown using molecular beam epitaxy on 4-in GaAs substrates. Fully selective double-recess and buried Pt-gate processes are employed to realize uniform and true enhancement-mode operation. Excellent dc and RF characteristics are achieved with threshold voltage, maximum drain current, extrinsic transconductance, and cutoff frequency of 0.3 V, 500 mA/mm, 850 mS/mm, and 128 GHz, respectively, as measured on 100-/spl mu/m gate width devices. The load pull measurements of 300-/spl mu/m gate width devices at 35 GHz yielded a 1-dB compression point output power density of 580 mW/mm, gain of 7.2 dB, and a power-added efficiency of 44% at 5 V of drain bias.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

A 16 DIP, 64 kbit, static MOS-RAM

A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.