共查询到20条相似文献,搜索用时 426 毫秒
1.
Rashad Ramzan Stefan Andersson Jerzy Dabrowski Christer Svensson 《Analog Integrated Circuits and Signal Processing》2009,61(2):115-127
In this paper a flexible RF-sampling front-end primarily intended for WLAN standards operating in the 2.4 GHz and 5–6 GHz
bands is presented. The circuit is implemented with on-chip Design for Test (DfT) features in 0.13 μm CMOS process. The front-end
consists of a wideband LNA, a sampling IQ down-converter implemented as switched-capacitor decimation filter, test attenuator
(TA), and RF detectors. The architecture is generic and scalable in frequency. It can operate at a sampling frequency up to
3 GHz and RF carrier up to 6 GHz with 2× subsampling. The selectable decimation factor of 8 or 16 makes the A/D conversion
feasible. The frequency response, linearity, and NF of the whole front-end have been measured. The power consumption of complete
RF front-end is 176 mW. The on-chip DfT features are helpful in reduction of overall test cost and time in volume production.
The measurement results show the feasibility of DfT approach for multiband radio receiver design using standard CMOS process. 相似文献
2.
In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality. 相似文献
3.
为实现低功耗信号传输,提出一种基于OFDM的IEEE 802.15.4g低功耗无线电频率(RF)收发器。该新型RF收发器电路由Tx BBA(基带模拟)、片上RF开关前端、Rx BBA及锁相环(PLL)构成,采用0.18?m CMOS技术制作,满足了IEEE 802.15.4g OFDM系统低功耗信号传输的需要。实际测试结果显示,相比传统的RF收发器,提出的RF收发器具有较低的功耗和良好的灵敏度,当电源电压为1.8 V时,Tx模式下会消耗14.7mA,Rx模式下会消耗15.7mA。 相似文献
4.
Baronti F. Lunardini D. Roncella R. Saletti R. 《Solid-State Circuits, IEEE Journal of》2004,39(2):384-387
This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-/spl mu/m CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution. 相似文献
5.
Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on-chip integrated inductor, a concise method to increase the Q factor has been ob tained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5 % compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's. 相似文献
6.
This paper describes a built-in self test technique for RF subsystems, using low-overhead on-chip detectors to calculate circuit specifications. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. The detector has small area overhead with a low-frequency output. A test chip was fabricated in a commercial 0.18 μm CMOS process. By using on-chip detectors in a loopback setup, both the system performance and specifications of the individual components can be accurately measured. Measurements show accurate prediction of system and component specifications. 相似文献
7.
This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz. 相似文献
8.
TD-LTE基站拉远射频单元作为4G网络的核心设备,其可靠性必须达到极高的水平。老化测试是提高射频设备可靠性的重要手段。本文针对这一要求为某司的所有类型射频拉远单元设计了一个通用,高效,可利旧的老化方案。 相似文献
9.
片上带隙基准电压源输出特性的偏差导致集成电路片上电源模块输出存在0~0.3 V的误差。文中对片上电源模块误差产生原因进行了研究,提出一种输出可调的带隙基准电压源外部电路设计方案来实现片上电源模块精确输出,并对电路参数确定方法进行了研究。该电路通过对片上带隙基准电压源后端分压电阻进行参数矫正实现对电源模块输出的精确调整。根据电流相等原理建立数学模型,通过测量两组固定参数电源模块输出数据,代入模型计算实现参数快速确定。实际测试数据证明,该电路可实现片上电源模块精确输出,误差仅为±0.02 V,满足实际应用需求。 相似文献
10.
This paper explores silicon CMOS on-chip spiral inductors performance degradation under high RF power. A novel methodology to calibrate and characterize on-chip spiral inductor with large signal inputs (high/medium power) is presented. Experiments showed 12% degradation of quality factor in a particular inductor design when 34 dBm RF power was applied. The degradation of quality factor of inductor can be attributed to a local self heating effect. Thermal imaging of such an inductor under high RF power validates the hypothesis. 相似文献
11.
Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthermore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting. 相似文献
12.
Mouna Karmani Chiraz Khedhiri Belgacem Hamdi Ka Lok Man Rached Tourki 《International Journal of Electronics》2013,100(6):837-850
Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker. 相似文献
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14.
In this paper, we have designed a double-gate MOSFET and compared its performance parameters with the single-gate MOSFET as RF CMOS switch, particularly the double-pole four-throw (DP4T) switch, for the wireless telecommunication systems. A double-gate radio-frequency complementary metal-oxide-semiconductor (DG RF CMOS) switch operating at the frequency of microwave range is investigated. This RF switch is capable to select the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the circuit elements (such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, and switching speed) required for the integrated circuit of the radio frequency sub-system of the DG RF CMOS switch and the role of these basic circuit elements are also discussed. These properties presented in the switches due to the double-gate MOSFET and single-gate MOSFET have been discussed. 相似文献
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从有理分式拟合方法出发,提出了用于射频CMOS平面螺旋电感2-π等效电路模型参数提取的新方法.通过比较提参后等效电路给出的S参数和实验测量的S参数,证明该方法的精度很高.此外,提参的策略非常直接,因此容易在CAD里面编程实现.提参得到的等效电路模型对于射频电路设计者来说也是非常有用的. 相似文献
18.
Hae-Moon Seo YeonKug Moon Yong-Kuk Park Dongsu Kim Dong-Sun Kim Youn-Sung Lee Kwang-Ho Won Seong-Dong Kim Pyung Choi 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(2):227-231
A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode 相似文献
19.
The effect of process induced variability in long global on-chip interconnects caused by critical dimension control and intrinsic fluctuation of transistor threshold voltage is analysed for current and voltage mode signalling. Projections in scaled CMOS technologies show that current sensing interconnects exhibit smaller mean delay and sensitivity to parameter fluctuations. The standard deviation of delay exhibits an increasing dependency on process variations at the low and high extremes of receiver to driver circuit resistance ratios. An experimental on-chip bus demonstrates the reduced delay variability in current sensing schemes. 相似文献
20.
《Solid-State Circuits, IEEE Journal of》2008,43(9):1951-1963