Length-constrained escape routing of differential pairs

In this paper, given a set of differential pairs (DPs) inside a single chip and the maximum tolerant length difference in a DP, a length-constrained escape routing problem in DPs is formulated. Firstly, the feasible merging connections and the feasible merging grids of all the DPs can be selected to satisfy the given length constraint and avoid routing an acute angle on a wire. Furthermore, based on the observation of the DP escape routing results from industrial boards, all the DPs can be divided into global and local DPs. By using two-phase escape routing, some local DPs can be escaped under the direction constraint and routed by using direct paths in direct escape routing and the unrouted local DPs and the global DPs can be escaped and routed by using obstacle-aware shortest paths in iterative obstacle-aware flow-based escape routing. Compared with Yan׳s escape router [11] and Li׳s escape router [12], the experimental results show that our proposed approach uses a shorter total wirelength under the larger length constraint and reduces 79.6% and 46.8% of the CPU time on the average to achieve 100% escape routability for six tested examples, respectively. Additionally, our proposed approach can obtain length-constrained escape routing results with the avoidance of routing an acute angle under the smaller length constraint for the tested example in the reasonable CPU time.     

Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement

We propose a net clustering based RT-level macro-cell placement approaches. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based on shared macro-cells and net criticality) yields clusters wherein each cluster has strongly interdependent nets. The circuit is modeled as a graph in which each vertex v represents a net and each edge (v,u) a shared cell between nets v and u. The net clusters are obtained by applying a clique partitioning algorithm on the circuit graph. Two approaches to generate placements at RTL are proposed: constructive (cluster growth) approach and iterative improvement (simulated annealing) based approach. In the constructive approach, a cluster-level floorplanning is performed and a cluster ordering is obtained. The cluster ordering is used by a constructive procedure to generate the physical placement. In the case of iterative improvement based approach, a good ordering of clusters is obtained using simulated annealing.We report experimental results for five RTL datapaths implemented in 0.35 m technology to demonstrate the efficacy of the proposed approaches. We compared the layouts produced by our approaches with those produced by Flint, an automatic floor planner in Lager IV Silicon Compiler [1]. For constructive placement approach, we obtained an average decrease of 43.4% in longest wirelength and 32.4% in total wirelength. The average area reduction is 7.3%. On the other hand, for the SA-based approach, we obtained an average decrease of 57.6% in longest wirelength and 42.2% in total wirelength. The average reduction in the bounding-box area is 12.3%. As expected, the SA-based approach yielded better optimization results, due to its ability to climb out of local minima.     

基于拓扑分析的多层通道布线算法

本文提出了一种基于拓扑分析的多层通道布线算法。算法把整个布线过程分成拓扑分层和物理布线两个部分。拓扑分层利用线段交叠图及模拟退火算法解决线段分层及通孔最少化问题，物理布线过程引入虚拟走线道解决交叉问题，再利用轮廓线跟踪的方法来决定最终确定各线段的布线位置。算法还解决了多层布线分层的管脚约束问题和相邻约束问题。实验结果表明，这是一种有效的方法。     

固定边框的多电压布图规划算法

多电压设计是应对SoC功耗挑战的一种有效方法,但会带来线长、面积等的开销。为减少线长、芯片的空白面积及提高速度,提出了一种改进的固定边框多电压布图方法.对基于NPE（Normalized Polish Expression）表示的布图解,采用形状曲线相加算法来计算其最优的布图实现,并通过增量计算方法来减少计算NPE及多电压分配的时间.为使所得布图解满足给定的边框约束,提出了一个考虑固定边框约束的目标函数,并采用删除后插入（Insertion after Delete,IAD）算子对SA求得布图解进行后优化.实验结果表明,和已有方法相比,所提出方法在线长和空白面积率方面有较明显优势,且所有电路在不同高宽比、不同电压岛数下均实现了极低的空白面积率（< <1%）.     

PIXAR: A performance-driven X-architecture router based on a novel multilevel framework

As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. In this paper, we present a performance-driven X-architecture router based on a novel multilevel framework, called PIXAR. To fully consider performance-driven routing and take advantage of the X-architecture, PIXAR applies a novel multilevel routing framework, which adopts a two-stage technique of top-down uncoarsening followed by bottom-up coarsening, with a trapezoid-shaped track routing embedded between the two stages to assign long, straight diagonal segments for wirelength reduction. We also propose a performance-driven X-Steiner tree algorithm based on the delaunay triangulations to construct routing tree for performance optimization. Compared with the state-of-the-art work, PIXAR achieves 100% routing completion for all circuits while reduced the net delay.     

宽带协方差矩阵的多字典联合稀疏表示DOA估计

为了直接处理相干宽带信号和提高其波达方向估计的分辨率,提出一种基于宽带协方差矩阵的多字典联合稀疏分解估计方法。首先,利用多个频率点处的过完备基对其协方差矩阵进行稀疏表示,然后形成多个字典的多测量矢量稀疏表示模型,最后通过多字典稀疏表示系数的联合稀疏约束以求解稀疏反问题的形式实现宽带信号的波达方向估计。对于均匀线阵结构,多字典协方差矩阵稀疏表示系数的联合稀疏性使其不再受空域采样条件的限制,既可通过增大阵元间距提高分辨率,而又无空域混叠现象。通过对噪声功率的预估计抑制噪声,提高了波达方向估计的稳健性。另外,该方法与信号协方差矩阵的秩无关,对相干信号和不相干信号都适用。仿真实验验证了该方法的有效性。      

Single- and multi- user uplink energy-efficient resource allocation algorithms with users’ power and minimum rate constraint in OFDMA cellular networks

In this paper, single- and multi- user Resource Allocation (RA) optimization problems considering transmit power and minimum rate constraint of Mobile Station (MS) for maximizing MS’ energy efficiency, measured as bits-per-joule (bpj), are addressed. Assume channel state information of all MSs is known by base station. We propose uplink RA algorithms, performing subcarrier assignment and power allocation, for optimizing bpj of MS in a single-cell OFDMA-based cellular network for both single- and multi- user scenarios. In the single-user case, we propose RA algorithms, which utilize the closed-form solution derived by applying Lambert-W function and an iterative approach based on Karush–Kuhn–Tucker conditions respectively to achieve optimal bpj of MS. In the multi-user case, centralized iterative multi-user RA algorithms for maximizing sum of MS’ bpj, performing joint subcarrier assignment and power allocation iteratively, are proposed by utilizing the proposed single-user RA schemes. In particular, tradeoffs between energy efficiency and spectral efficiency are fully investigated, and the influence of MS’ power and minimum rate constraints on bpj performance is also studied. The effectiveness of proposed algorithms is presented by numerical experiments. Numerical results demonstrate the proposed algorithms can enhance bpj significantly with limited loss of total throughput compared to the sum-rate maximization algorithm (in Moretti et al., IEEE Trans Veh Technol 60(4):1788–1798, 2011).     

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.     

利用无监督学习的RIS辅助毫米波通信系统鲁棒传输设计

本文研究了利用无监督学习的可重构智能表面（reconfigurable intelligent surface,RIS）辅助毫米波大规模多输入多输出（multiple input multiple output,MIMO）下行传输设计。首先,针对发送端信道状态信息（channel state information,CSI）非理想场景,推导了RIS辅助的毫米波下行传输系统平均频谱效率闭式上界。进一步,考虑实际系统硬件受限的条件,本文采用基于离散傅里叶变换（discrete Fourier transform,DFT）码本的模拟预编码,且RIS各反射单元仅能取有限的离散相移值。在此基础上,以所推导的平均频谱效率上界最大化为目标,提出一种基于无监督学习的发送端混合预编码、接收端数字合并以及RIS反射单元相移联合设计方法。所提方法采用两阶段无监督学习模型,分别生成RIS反射单元相移与发送端混合预编码,而接收端数字合并矩阵则采用最小均方误差（minimum mean squared error,MMSE）准则生成。同时,本文针对该模型提出了一种高效的分段训练方法。该训练方法分别对生成RIS反射...     

Evolutionary algorithm for data association and IMM-based target tracking in IR image sequences

Simultaneous tracking of multiple maneuvering and non-maneuvering targets in the presence of dense clutter and in the absence of any a priori information about target dynamics is a challenging problem. A successful solution to this problem is to assign an observation to track for state update known as data association. In this paper, we have investigated tracking algorithms based on interacting multiple model to track an arbitrary trajectory in the presence of dense clutter. The novelty of the proposed tracking algorithms is the use of genetic algorithm for data association, i.e., observation to track fusion. For data association, we examined two novel approaches: (i) first approach was based on nearest neighbor approach and (ii) second approach used all observations to update target state by calculating the assignment weights for each validated observation and for a given target. Munkres’ optimal data association, most widely used algorithm, is based on nearest neighbor approach. First approach provides an alternative to Munkres’ optimal data association method with much reduced computational complexity while second one overcomes the uncertainty about an observation’s source. Extensive simulation results demonstrate the effectiveness of the proposed approaches for real-time tracking in infrared image sequences.     

Switched-Diversity Approach for Cognitive Scheduling

This article investigates the scheduling of secondary users in a spectrum-sharing cognitive environment under the primary user’s outage probability constraint. A switched-diversity combining approach to schedule the secondary users is explored. Specifically, switch-and-examine, switch-and-stay, selection-combining, and post-selection scheduling algorithms are investigated. Secondary users’ average performance measures are derived for the scheduling algorithms and compared against those of a single-user cognitive system. Results of this work illustrate the trade-off between the complexity of a scheduling algorithm and its average performance.     

Multiple-Constraint-Aware RWA Algorithms Based on a Comprehensive Evaluation Model： Use in Wavelength-Switched Optical Networks

Because of explosive growth in Internet traffic and high complexity of heterogeneous networks,improving the routing and wavelength assignment (RWA) algorithm in underlying optical networks has become very important.Where there are multiple links between different the node pairs,a traditional wavelength-assignment algorithm may be invalid for a wavelength-switched optical networks (WSON) that has directional blocking constraints.Also,impairments in network nodes and subsequent degradation of optical signals may cause modulation failure in the optical network.In this paper,we propose an RWA algorithm based on a novel evaluation model for a WSON that has multiple constraints.The algorithm includes comprehensive evaluation model (CEM) and directional blocking constraint RWA based on CEM (DB-RWA).Diverse constraints are abstracted into various constraint conditions in order to better assign routing and wavelength.We propose using the novel CEM to optimize routing according to an assessed value of constraints on transmission performance.This eliminates the effects of physical transmission impairments in a WSON.DB-RWA based on CEM abstracts directional blocking conditions in multiple links between network nodes into directional blocking constraints.It also satisfies rigorous network specifications and provides flexibility,scalability,and first-fit rate for the backbone,especially in multiple links between WSON nodes.     

A new iterative method for analysing nonlinear photonic-crystal structures

The article presents an efficient iterative method for analysing non-linear photonic crystals. The new approach is used for analysing a frequency converter constructed with a 2D pillar-type photonic crystal waveguide structure. The considered converter uses the non-linear properties and the compound waveguide structure. The analysis is based on the iterative resolution of two relationships between incident and reflected volume-waves. The reflection operator is expressed using Hankel functions. Numerical results have been obtained with moderate CPU time and memory requirement. Simulations obtained are in agreement with recent published results.     

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.     

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach

Three-dimensional (3D) ICs have the potential to reduce the interconnect delay, but thermal problem becomes one of the most serious challenges. In this paper, we proposed an efficient thermal aware 3D placement algorithm,which takes use of quadratic uniformity modeling approach. In this model, cell distribution and thermal dissipation are integrated and formulated as a quadratic function through discrete cosine transformation (DCT) with wirelength optimization. Quadratic programming method is utilized to solve the unified quadratic objective function. We update the unified cell distribution and thermal dissipation with each step of the iterative placement process. Thermal distribution was considered enough during placement process even when a cell was moved. To save time, two fast methods to reflect thermal change were proposed for thermal distribution computation. The experimental results show our thermal aware 3D placement algorithm is efficient with about 3% reduction in average temperature and 15% in max temperature but a little perturbation on wire length.     

Window-constrained interconnect-efficient progressive edge growth LDPC codes

One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature of their iterative belief propagation decoding, making them amenable to efficient hardware implementation. However, for an arbitrary code construction, the random-like connections between the code's Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem of dense connections between processing nodes. The approach is based on controlling the maximum connection length between processing nodes in order to make fully parallel implementation feasible. The proposed algorithm offers a good compromise between error correction performance and decoder complexity. Simulation results and FPGA-based implementation comparisons are presented to demonstrate the advantages of the proposed LDPC code constructions, and it is shown that, with proper window-constrained node placement design, an improvement of up to 40% in interconnect efficiency is achievable without any significant degradation in error correction capability.     

Weighted evidence combination based on degree of credibility and certainty

To overcome the invalidation problem of Dempster rule with high conflict,a weighted combination method based on degree of credibility and certainty was proposed.Firstly,the cosine similarity was modified to hold the ability to measure the evidence conflict when multi-subset focal elements were included,followed by the building of evidence credibility model.Secondly,the evidence certainty model based on precision and entropy was presented,which can both reflect the evidence’s degree of multi-subset focal elements and the dispersion degree of probability assignment.Then the weighted coefficient was determined by credibility and certainty.Finally,the normalized weighted coefficient was used to average the basic probability assignment,and the final combination result can be obtained according to Dempster rule.Numerical examples show that,compared with other traditional weighted combination methods,the proposed approach has made better performance in reducing conflict and accelerating convergence.     

An efficient heuristic force directed placement algorithm based on partitioning

An efficient heuristic force directed placement algorithm based on partitioning is proposed for very large-scale circuits. Our heuristic force directed approach provides a more efficient cell location adjustment scheme for iterative placement optimization than the force directed relaxation (FDR) method. We apply hierarchical partitioning based on a new parallel clustering technique to decompose circuit into several level sub-circuits. During the partitioning phase, a similar technique to ‘terminal propagation’ was introduced so as to maintain the external connections that affect cell adjustment in sub-circuit. In these lowest level sub-circuits, the heuristic force directed algorithm is used to perform iterative placement optimization. Then each pair of sub-circuits resulted from bisection combine into a larger one, in which cells are located as the best placement state of either sub-circuits. The bottom-up combination is done successively until back to the original circuit, and at each combination level the heuristic force directed placement algorithm is used to further improve the placement quality. A set of MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks is experimented and results show that our placement algorithm produces on average of 12% lower total wire length than that of Feng Shui with a little longer CPU time.     

约束条件下的结构化高斯混合模型及非平行语料语音转换

提出一种约束条件下的结构化高斯混合模型及非平行语料语音转换方法.从源与目标说话人的原始非平行语料中提取出少量相同音节,在结构化高斯混合模型的训练过程中,利用这些相同音节包含的语义信息及声学特征对应关系对K均值聚类中心进行约束,并在（Expectation Maximum,EM）迭代过程中对语音帧属于模型分量的后验概率进行修正,得到基于约束的结构化高斯混合模型（Structured Gaussian Mixture Model with Constraint condition,C-SGMM）.再利用全局声学结构（Acoustic Universal Structure,AUS）原理对源和目标说话人的约束结构化高斯混合模型的高斯分布进行匹配对准,推导出短时谱转换函数.主观和客观评价实验结果表明,使用该方法得到的转换后语音在谱失真,目标倾向性和语音质量等方面均优于传统的结构化模型语音转换方法,转换语音的平均谱失真仅为0.52,说话人正确识别率达到95.25%,目标语音倾向性指标ABX平均为0.82,性能更加接近于基于平行语料的语音转换方法.     

Differential Time Signaling Data-Link Architecture

A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.