FPGA多标准可配置Ⅰ/O接口电路设计

随着FPGA使用的工艺尺寸逐渐减小和芯片设计技术的逐步完善,FPGA与ASIC之间性能差异也逐渐减小.正因为如此,越来越多的研究开始集中于FPGA中CLB的内部结构与FPGA的布线算法优化.但是,针对FPGA多标准兼容可配置I/O的研究却极少.文章提出了一种能够同时满足多标准接口应用与可动态配置要求的I/O接口电路结构,并已将其应用在某款采用华虹NEC 0.22,μm工艺的FPGA芯片中.仿真证明,该结构满足设计要求,接口电路性能优于Xilinx的类似结构.     

基于DSP+FPGA的高速数字信号处理平台的电源设计

介绍了一种高速数字信号处理平台的电源设计实现方案,主要是基于FPGA DSP的结构实现高速数字信号处理。该方案采用先进的FPGA,DA转换器和DSP芯片,通过对DSP芯片和FPGA芯片及DA芯片的正确供电和电源监控来实现具有通用性、可扩充性的硬件平台,并对电源设计中的多项关键参数进行分析与阐述。     

基于DSP+FPGA的高速数字信号处理平台

本文介绍了一种高速数字信号处理平台的实现方案,主要是基于FPGA DSP的结构来实现高速数字信号处理.该方案采用先进的FPGA和DSP芯片,借鉴了软件无线电的思想,通过DSP芯片对FPGA芯片的动态配置来实现具有通用性、可扩充性的硬件平台,并对其硬件结构和软件工作流程进行了阐述.     

FPGA在恶劣电磁环境下的抗干扰设计

在恶劣电磁环境下,对现场可编程逻辑阵列(FPGA)工作稳定性影响较大的是外界杂波脉冲和毛刺信号.从FPGA芯片内部设计和外部设计两方面介绍了提高FPGA芯片工作稳定性的一些措施.     

FPGA多标准可配置I／O接口电路设计

随着FPGA使用的工艺尺寸逐渐减小和芯片设计技术的逐步完善，FPGA与ASIC之间的性能差异也逐渐减小。正因为如此，越来越多的研究开始集中于FPGA中CLB的内部结构与FPGA的布线算法优化。但是，针对FPGA多标准兼容可配置I／O的研究却极少。文章提出了一种能够同时满足多标准接口应用与可动态配置要求的I／O接口电路结构，并已将其应用在某款采用华虹NEC0．22μm工艺的FPGA芯片中。仿真证明，该结构满足设计要求，接口电路性能优于Xilinx的类似结构。     

软件

RTL工具提升FPGA性能Mentor Graphics Precision RTL综合工具通过配置特定的结构算法,增强精确的时序驱动综合技术和采用多种优化技术,使ProASIC Plus系列FPGA的时钟频率平均提升了18%。PrecisionRTL综合工具完全集成在Actel的Libero6.0 IDE中,让设计人员可设定更高的频率,在现有的设计流程中实现更高性能提升。Mentor Graphicshttp://www.mentor.com进行射频仿真的EDA工具EDA工具VeloceRF可对射频芯片和系统级封装进行快速的全芯片射频建模,所带的感应系数建模器可支持提取螺线管电感、变压器和RF互连的RLCk参数。此外…     

无线发码通用遥控编码芯片的ASIC设计

提出了一种通用遥控编码芯片的设计方案,阐述了芯片功能原理,对各模块的主要电路进行了设计、分析,其中给出了一些设计巧妙的电路结构,整个设计采用全原理图输入方式,最大程度地简化了电路,最后对整个方案进行了仿真.这种通用遥控编码芯片可以完成对遥控电路发送端数字基带信号的编码.外围电路简单,大大简化了板极电路的复杂度、成本低,可靠性高.这种编码芯片可以应用在家用电器遥控、车库门控制、防盗报警系统等多种遥控场合.FPGA是一种新型的高密度大容量的PLD.整个方案在FPGA中通过了原型验证.     

在65nm Cyclone Ⅲ FPGA中实现低功耗

传统上,人们总是期望新一代FPGA具有更好的特性和性能.然而,设计工程师必须将这些新特性和高性能集成在与上一代产品相同、甚至更小尺寸的芯片上,并要保持芯片功耗不变.此外,某些应用还必须要满足一些特殊的功耗要求.结果,功耗在设计工程师的FPGA选择标准中扮演了越来越重要的角色.     

SRAM型FPGA系统的设计与实现

对FPGA芯片、通用DSP芯片、专用DSP芯片及ASIC在实现数字信号处理方面的差异进行了比较,指出了FPGA在实现数字信号处理方面的优势,给出了FPGA在信号处理方面的设计新方法,最后对常用的分布式算法以及在FPGA中的实现结构进行了分析.     

面向FPGA芯片开发的测试方法设计与实现

针对自主研发的SOI-CMOS工艺FPGA芯片VS1000,开发出一种FPGA测试工具(VVK)软件系统.VVK是借助Verilog HDL描述电路和UCF约束电路的特性开发并实现的全自动测试方法.其意义在于解决了设计FPGA芯片过程中面临的最冗繁棘手的验证和测试难题,可以实现FPGA全芯片、内部各种逻辑模块的功能结构的验证和测试.该工具可以用于FPGA流片前的行为级、晶体管级的仿真和验证、FPGA圆片测试、以及FPGA芯片抗辐照测试.验证和测试的结果证明了这套方法的正确性、高效性,同时这种测试方法也适用于其他架构FPGA的测试.     

Design and analysis of a dynamically reconfigurablethree-dimensional FPGA

This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied     

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This paper describes such an FPGA routing architecture, called the multibit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, compared to conventional FPGA routing architectures, the multibit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall FPGA area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections.     

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70× faster than FPGA tools, with a circuit speed 5.8× slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range in the number of processor cores. We also demonstrate tool scalability to very large circuits, synthesizing, placing, and routing a ≈1.6 million gate random circuit in 54 min.     

Design and Implementation of Viterbi Decoder with FPGAs

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.     

The effect of LUT and cluster size on deep-submicron FPGA performance and density

In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs (Betz et al. 1997) we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. We use a fully timing-driven experimental flow (Betz et al. 1997), (Marquardt, 1999) in which a set of benchmark circuits are synthesized into different cluster-based (Betz and Rose, 1997, 1998) and (Marquardt, 1999) logic block architectures, which contain groups of LUTs and flip-flops. Across all architectures with LUT sizes in the range of 2 to 7 inputs, and cluster size from 1 to 10 LUTs, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that clustering small LUTs (sizes 2 and 3) produces better area results than what was presented in the past. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 3-10 provides the best area-delay product for an FPGA.     

DES算法IP核设计

通过分析数据加密标准(DES)的算法结构，给出了一种电路实现模型。基于A1tera公司的FPOA系列器件，给出算法IP核的设计，最后对该IP核进行了分析，给出它的性能参数。     

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.     

Guest Editors' Introduction

In this paper we present our studies for implementing complex DSP and Telecom systems in FPGAs. We analyse suitability of FPGA device architectures for implementing complex algorithms. Here we use a Viterbi algorithm as a deeper case study. Different architectural strategies for implementations are discussed and analysed with the special emphasis on practical FPGA implementations. Speed performance, easy routability and minimisation of inter-chip communication are used as design criteria. Viterbi decoder, constraint length seven, was designed and simulated with VHDL in Synopsys and Mentor tool environments and further implemented on four Xilinx 4028EX devices using trace-back based architecture. Also partitioning aspects of the decoding algorithm are presented and analysed.

     

The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices

This paper describes the architectural configuration and various design trade-offs of the Electrically Programmable Analog Circuit (EPAC^TM), an expert-cell approach to meeting the market needs for an analog counterpart to the digital FPGA. The paper provides an overview of the technology, discusses architectural issues, and describes the internal operation of the first commercial EPAC devices. The paper concludes with various application examples and performance measurements.     

Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

System on a chip (SoC) creates massive design challenges for SoC‐based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software‐Defined System‐on‐Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA‐CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA‐CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA‐CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA‐CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long‐term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints.