Effect of Soliton Propagation in Fiber Amplifiers

The propagation of optical solitons in fiber amplifiers is discussed by considering a model that includes linear high order dispersion, two-photon absorption, nonlinear high-order dispersion, self-induced Ramam and five-order nonlinear effects.Based on traveling wave method, the solutions of the nonlinear Schrodinger equations, and the influence on soliton propagation as well as high-order effect in the fiber amplifier are discussed in detail.It is found that because of existing five-order nonlinear effect ,the solution is not of secant hyperbola type, but shows high gain state of the fiber amplifier which is very favourable to the propagation of solitons.     

ANALYSIS OF INTERNALLY GENERATED NOISE OF BIOELECTRIC AMPLIFIERS

This papenr deals with internally generated noise of bioelectric amplifiers that are usually used for processing of bioelectric events.The main purpose of this paper is to present a procedure for analysis of the effects of internal noise generated by the active circuits and to evaluate the output noise of the author‘s new designed bioelectric amplifier that caused by internal effects to the amplifier circuit itself in order to compare it with the noise generated by conventional amplifiers.The obtained analysis results of internally generated noise showed that the total output noise of bioelectric active circuits does not increase when some of their resitors have a larger value.This behavior is caused by the different transfer functions for the signal and the respective noise sources associated with these resistors.Moreover,the new designed bioelectric amplifier haws an output noise less than that for conventional amplifiers.The obtained analysis results were also experimentally verified and the final conclusions were drawn.     

Design of Si—bipolar Monolithic Main Amplifier IC for Optical Fiber Receivers

A broadband amplifer with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study.Making use of the basic amplifier cells.a main amplifier IC for optical-fiber receivers is deliberated.By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range.They are maximum voltage gain of 42 dB,ths bandwidth of 730 MHz,the input signal(Vp-0)range from 5 mV to 1V,the output amplitude about 1V,the dynamic range of 46 dB.The designed circuit containing no inductance and large caacitance will be convenient for realizing integration.A monolithic integrated design of 622Mb/s main amplifier is completed.     

Theoretical study on pulse-shaping of Stokes pulse with steep leading edge by two Brillouin amplifiers

A novel configuration of two Brillouin amplifiers, which contains a main amplifier combined with a reshaping amplifier, is suggested to control pulse shape of Stokes pulses with steep leading edge. Dependences of pulse shapes on several param- eters are numerically simulated. By changing the distance between the two amplifiers, the leading edge of amplified pulses can be finely adjusted. Smooth and symmetrical pulses or pulses with slow leading-edge are achieved. Theoretical re- searches prove that this system is fit for shaping pulses with steep leading edge, especially, for controlling leading edge of pulses. The results provide useful and necessary theoretical basis and guidance for the future experimental research.     

TD-SCDMA： Spectrum Modeling, Experimental Verification of Power Amplifier Nonlinearity

RF Power amplifiers （PA） are critical components in Time division-Synchronous code division multiple access （TD-SCDMA） systems, and PA nonlinearity is one of the main concerns in RF power amplifier designs. This paper presents experimental verification of the spectrum modeling of a RF power amplifier in TD-SCDMA system based on our previous work. The results verify the theoretical spectrum model we derived closely fits the experimental measurements.     

Design and simulation of optoelectronic oscillator with micro ring resonator and radio frequency amplifier modelling at 110 GHz

There is an increasing need for high performance oscillators as the faster transmission networks demand for high frequency signals. Opto-electronic oscillators (OEO) enable us to make better oscillators in terms of size, weight and power. In this paper, photonic integration is proposed for realizing the OEO with micro ring resonator (MRR) and radio-frequency (RF) amplifiers of monolithic microwave integrated circuit (MMIC), which can be used for generating 110 GHz sine wave. The OEO architecture is proposed and block diagram developed considering Silicon based MRR and three-stage RF amplifier based on GaN high-electron-mobility transistor (HEMT). A simulation model is developed according to the Klein model of MRR and is validated against the calculated performance parameters. MRR dimensions are calculated as with silicon on insulator (SOI) technology and a radius 5.27 μm for the device is derived. Free spectral range (FSR) of 48.52 nm and filter rejection ratio of 16.79 dB are obtained for this device. The proposed RF amplifier is modelled with GaN parameters derived from high frequency pinch-off model and with power amplifier considerations. The gain for this amplifier is obtained as 10.6 dB. The OEO design is developed in this project in such a way that the system can be manufactured with the existing methods.     

An Envelope Hammerstein Model for Power Amplifiers

In this paper, an envelope Hammerstein （EH） model is introduced to describe dynamic input -output characteristics of RF power amplifiers. In the modeling approach, we use a new truncation method and an established nonlinear time series method to determine model structure. Then, we discuss the process of model parameter extraction in detailed. Finally, a 2 W WCDMA power amplifier is measured to verify the performance of EH model, and good agreement between model output and measurement result shows our model can accurately predict output characteristic of the power amplifier.     

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

正A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers.The enhancer utilizes the class-AB input stage to improve current efficiency,while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier.During the slewing period,the enhancer detects input differential voltage of the amplifier,and produces external enhancement currents for the amplifier,driving load capacitors to charge/discharge faster.Simulation results show that,fora large input step,the enhancerreduces settling time by nearly 50%.When the circuit is employed in a sample-and-hold circuit,it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB.The proposed circuit is very suitable to operate under a low voltage(1.2 V or below) with a standby current of 200μA.     

射频线性功放的偏置电路对线性度影响的理论分析和改善方法

Based on the Gummel-Poon model of BJT, the change of the DC bias as a function of the AC input signal in RF linear power amplifiers is theoretically derived, so that the linearity of different DC bias circuits can be interpreted and compared. According to the analysis results, a quantitative adaptive DC bias circuit is proposed, which can improve the linearity and efficiency. From the simulation and test results, we draw conclusions on how to improve the design of linear power amplifier.     

Double Clad Er-doped Fiber Amplifier

Presented is a theoretical study of double-clad Er-doped fiber power amplifier（EDFA）. Two kinds of double clad fibers（DCF） with rectangular and ＂flower＂ inner clad shapes are studied, and these fibers have different coupling constants and propagation losses. We calculate the effective pump power absorption ratio along the fiber with different coupling constants from the first cladding to the doped core and with different propagation losses for the power in the inner cladding. Then the gains of the double clad Er-doped fiber amplifiers versus fiber lengths are calculated using the EDFA model based on propagation and rate equations of a homogeneous, two-level medium.     

Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.     

Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers

This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-mum CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/mus average slew rate, by only dissipating 90 muW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kOmega // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier.     

A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-μm CMOS technology. Qiang Li received the B.S. degree and the M.Sc. degree in College of Microelectronics and Solid-state Electronics from University of Electronic and Technology Science of China (UESTC), in 2002 and 2005, respectively. His main research interest is low-voltage low-power analog ICs and power switch management ICs. From 2005, he joined the o2micro as an analog IC designer. Jun Yi un Yi received the B.S. degree and the M.Sc. degree, both in Microelectronics, from University of Electronic Science and Technology of China, Chengdu, China, in 2001 and 2004, respectively. He is currently working toward the Ph.D. degree at The Hong Kong University of Science and Technology, Hong Kong, China. His research interests include low-voltage low-power analog and mixed-signal integrated circuits, low-power power management system, with current emphasis on ultra-low-power power management and signal processing integrated circuits for micro-sensor, RFID, and biomedical applications. Bo Zhang was born in Chongqing, China, on May 26, 1964. He received his B. Tech. degree in electronic engineering from Beijing Institute of Technology, China in 1985, the M. Tech. degree from the University of Electronic Science and Technology of China in 1988. From 1988 to 1996, he worked on power semiconductor devices research and development at the University of Electronic Science and Technology of China. From 1996 to 1999, he was a Visiting Professor at Virginia Polytechnic Institute and State University, Blacksburg, U.S.A., where his research activities include device simulations, power semiconductor cryogenics, SiC power devices, and other Si-based power semiconductor devices. Since returning to the University of Electronic Science and Technology, China, in Nov. 1999, he has worked on power devices and smart power ICs. He is currently a Professor and has published more than 100 papers in the international conferences and journals. Zhaoji Li, professor, the director of IC design center of University of Electronic Science and Technology of China (UESTC).     

适合宽范围电容负载的三级运放

结合精确度和稳定性的要求提出了一种适合宽范围电容负载的CMOS运放.在多径嵌套式密勒补偿结构中加入一个抑制电容得到适合各种电容负载的稳定性.为了证实稳定性的提高对该结构进行了理论分析并计算得出数学表达式.基于这种新的频率补偿结构,利用CMOS 0.7μm工艺模型设计了样品芯片.测试结果表明:该运放可以驱动从100pF到100μF负载电容,直流增益为90dB,最小相位裕度为26°;该运放在100pF负载情况下单位增益带宽为1MHz,使用抑制电容仅为18pF.     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

用于低功耗三级放大器的嵌套式密勒有源电容频率补偿技术

提出了一种新的用于低功耗,节省面积的三级放大器频率补偿技术.该技术将有源电容进行嵌套连接从而克服了传统的嵌套式密勒补偿与反嵌套式密勒补偿的缺点.当将这一技术用标准的0.35μm工艺设计成电路并负载150pF电容时,放大器实现了105dB直流增益,3.3M的增益带宽积,68°相位裕度以及2.56V/μs的平均转换速率.而这一切的实现是在2V电源电压仅消耗40μW的功耗以及使用了很小的补偿电容.     

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.     

Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads

In this paper, a dual-Miller parallel compensation (DMPC) technique for low-power three-stage amplifier is presented with detailed theoretical analysis. A feedback network realized by capacitor and transconductance is added between the first and third stage, which improves significantly the performance when driving large capacitive loads. Furthermore, it is found to be stable for a wide range of capacitive loads. The proposed DMPC amplifier has been implemented in a 0.13-μm CMOS process and the chip area is 0.17×0.11 mm². It achieves a 0.87 MHz gain-bandwidth product by consuming a total current of 41 μA. The DMPC amplifier is verified to be stable when the load capacitor ranges from 8 pF to 2 nF.     

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain

A fully differential operational amplifier has been designed and fabricated for a novel high resolution and high frequency analog-to-digital converter(>12-bit). The amplifier mainly consists of folded cascode structure with current source as output loads and common-mode feedback circuits. The technique of feedforward compensation is used in order to improve the settling time and gain bandwidth (GBW) of this amplifier. This amplifier is integrated in 0.8 mm BiCMOS process with an active die area of 0.1 mm². The DC gain of this amplifier is 90 dB. The GBW and phase margin of this amplifier is 900 MHz and 47°, respectively. The power dissipation is minimized by using BiCMOS technology and is about 25 mW for 2 pF load capacitance. This level of performance is competitive with CMOS and BiCMOS operational amplifier circuits previously reported by nearly two orders of magnitude.Ecole Polytechnique of the University of Montreal