基于FPGA的多路数字立体声E1接入设计

介绍了一种用可编程器件FPGA实现多路数字立体声与E1之间的速率转换、码型变换及时钟恢复等功能,以实现广播电台的多路立体声信号在一个E1信道中传输.此外,以可编程器件RFPGA芯片为设计基础,介绍每个模块的具体实现原理及方法,给出了相应的设计程序及作者在设计时所用到的相关芯片.该设计方案为将来实现广播电视网音频接入到标准的SDH网络提供一种简便、实用及性价比高的接入设备.     

市场指南

AMD下属的Vantis(威特信)公司(总部在美国加州Sunnyvale)专门从事开发可编程逻辑器件,它的产品包括现场可编程门阵列(FPGA)、复杂可编程逻辑器件(CPLD)、简单可编程逻辑器件(SPLD)以及设计软件。最近,Vantis宣布推出VF1系列FPGA器件及Direct-DesignTM设计软件。和其它FPGA的开发策略不同,VF1是以软件为中心设计器件的结构,是先有软件后有可编程门阵列器件,因此软件和硬件都便于用户使用。Vantis的软件工具Dcsign-DirectTM和用户已经拥有的第三方EDA软什工具(例如原理图输入、捕捉及模拟、     

可编程逻辑器件现状及发展趋势

可编程逻辑器件现状可编程逻辑器件发展很快,已经从20年前几百门的PAL/GAL发展到现在的超过300万门的FPGA,已拥有可以提供足够系统集成容量的密度、增强的嵌入系统能力、功能集合及许多其他特性的新器件。新的开发工具提供了对这些新器件的支持,并具有以更高的生产率实现数百万门电路设计的能力。与新芯片及软件相配合的是带知识产权的系统级设计模块解决方案,它们的参数可由用户自定。芯片、软件及知识产权功能构成了完整的可编程解决方案,可编程逻辑已成为系统集成的平台。1、全球可编程逻辑器件市场现状根据IDC的数据,可编程…     

邮电新书讯

1.12122《可编程器件应用开发指南》作者路而红主编定价21.00元本书结合可编程器件的最新发展,介绍了实用的数字可编程器件ispLSI系列器件和模拟可编程器件ispPAC系列器件的原理及其性能,并介绍了简单易学的开发语言ABEL-HDL、方便快捷的开发工具ispDesignEXPERT和PAC-Design的使用。书中还系统地介绍了数字和模拟可编程器件的应用实例,具有一定的实用价值。本书可作为从事电子产品开发和生产的工程技术人员的技术参考资料,也可作为大专院校电子工程类专业的教学参考书。2.12280《光纤通信技术》(北京市教委精品教材)作者孙学康张…     

业界第一个混合信号PLD

莱迪思半导体公司近日宣布推出其创新的PowerPACTM器件。该器件是业界第一片混合信号可编程逻辑器件(PLD),它内含在系统可编程的模拟和逻辑组块,能提供经过优化的电源管理功能,这一功能对如今的多电源电子系统是至关重要的。该器件集成了可编程逻辑、电压比较器、参考电压及高电压的场效应管驱动器,支持单芯片可编程供电定序与监控。     

用CPLD实现码速变换

本文介绍利用可编程器件ＣＰＬＤ实现计算机异步速率(５７．６ｋ、２３０．４Ｋ、４６０．８ｋ等)向相邻标准速率(６４k、２５６ｋ、５１２ｋ等)变换的原理及设计方法,为实现ＰＣ机异步数据与同步设备相连接提供了一种简易的实现方法。     

基于ATE的可编程逻辑器件测试方法

集成电路发展模式已从软编程、硬编程到软硬双编程方向发展,可编程器件已成为时代主流,对可编程器件的测试需求越来越多。首先介绍了可编程器件的概念和分类,然后针对目前主流的自动测试设备(ATE)做了介绍,接着详细描述了各种可编程器件的测试方法。该方法具有较强的通用性,可广泛应用于各种PLD、PROM、CPLD、FPGA等可编程器件的测试,对于实现可编程器件的产业化测试具有一定意义。     

可编程逻辑器件在电力电子控制技术中的应用

随着电力电子技术的发展,电力电子控制技术逐渐向智能化和高效性方向发展。在电力电子控制技术中的信号处理领域中可编程逻辑器件得到了广泛的应用,可编程逻辑器件具有处理速度快的特点。文章对可编程逻辑器件的特点和应用进行了分析,结合可编程逻辑器件的高速度和高集成性的特点,提出了可编程逻辑器件在电力电子控制技术中的应用的设计方案,对可编程逻辑器件在电力电子控制技术中应用进行了分析和研究。     

新一代FPGA逻辑器件ispXPGA及其应用

新一代现场可编程器件ispXPGA由于将EEPROM集成在基于SRAM工艺的现场可编程器件中 ,因而充分发挥了EEPROM的非易失特性和SRAM的重配置特性 ,同时还集成了诸多接口标准和IP核 ,从而解决了传统现场可编程器件的诸多难点 ,是真正的单片电子设计系统。文中介绍了ispXP GA器件的结构特点 ,同时给出了其选择型号及软件工具     

用户可编程门阵列

第一代的可编程逻辑器件(PLD)以1片器件代替5至10片TTL器件,最新一代可编程器件FPGA可以代替40至400片小规模集成电路。本文介绍四种可编程门阵列的基本结构和主要性能,并给出采用该类器件设计电路的编程技术。     

31位低频声表面波可程序匹配滤波器

报道了３１位声表面波可程序匹配滤波器的结构、设计和性能参数。声表面波可程序抽头延迟线是近年来快速发展的直扩技术广泛应用的一种器件。它的强大信号处理能力和极高的运算速度，使得直扩序列信号的快速同步及匹配滤波较传统的技术大为简化。文章报道的３１位声表面波低频可程序抽头延迟线是一种用于扩频抗干扰通信系统所用的关键信号处理器件。在研制过程中，采用的ＣＯＭＳ／ＳＯＳ等新技术以及分裂抽头等新设计，使器件的时钟速率和主旁瓣比关键技术指标获得了较大的提高，完全满足系统要求     

Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.     

A novel 2-D programmable photonic time-delay device formillimeter-wave signal processing applications

We describe a novel programmable photonic true time-delay device that has the properties of low loss, inherent two dimensionality with a packing density exceeding 25 lines/cm², virtually infinite bandwidth, and is easy to manufacture. The delay resolution of the device is on the order of femtoseconds (microns in space) and the total delay exceeds one nanosecond (30 cm in space)     

Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance

A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.     

A merged pipe organ binary-analog correlator

The design of a 96-stage, programmable binary-analog correlator is described. An array of charge coupled device (CCD) delay lines of differing lengths perform the delay and sum function. Merging of several CCD channels is employed to reduce the active area. This device architecture allows simplified output detection while maintaining good device performance at high speeds (5-10 MHz). Experimental results indicate a 50 dB broad-band dynamic range and excellent agreement with the theoretical processing gain (19.8 db) when operated at a 6 MHz sampling frequency as a sequence matched filter pseudorandom noise.     

Delay-locked loop technique for temperature stabilisation ofinternal delays of CMOS FPGA devices

A delay-locked loop (DLL) technique for use with typical CMOS field programmable gate array (FPGA) devices is presented. It allows for temperature stabilisation of the internal delays of the devices, especially when the digital delay lines are designed. The voltage V_cc supplying the FPGA device is varied within a limited range by the DLL to stabilise the internal delays of the device under changes in the ambient temperature. The method is illustrated by presenting results of the realisation of an interpolating time counter with 200 ps resolution, implemented on a single CMOS FPGA device     

Adaptive delay estimation for partitioning-driven PLD placement

This paper describes the application of weighted partitioning techniques to timing-driven placement on a hierarchical programmable logic device. We discuss the nature of placement on these architectures, the details of applying weighted techniques specifically to the programmable logic device (PLD) CAD flow, and introduce the new concept of adaptive delay estimation using phase local to increase performance. Empirical results show that these techniques, in a fully complete system with large industrial designs, give an average 38.5% improvement over the unimproved partitioning-based placement tool. Approximately two-thirds of this benefit is due to our improvements over a straightforward weighted partitioning approach.     

Programmable group-delay module using binary polarization switching

We demonstrate the first programmable group-delay module based on polarization switching. With a unique binary tuning mechanism, the device can generate any differential group delay value from -45 to +45 ps with a resolution of 1.40 ps, or any true-time-delay value from 0 to 45 ps with a resolution of 0.7 ps. The delay varying speeds for both applications are under 1 ms and can be as fast as 0.1 ms. We evaluate both the dynamic and static performances of the device while paying special attention to its dynamic figures of merit for polarization-mode dispersion emulation and compensation applications. Our experiment shows that the device exhibits a negligible transient-effect induced power penalty (<0.2 dB) in a 10-Gb/s nonreturn-to-zero system.     

声表面波可程序抽头延迟线研究

报道声表面波可程序抽头延迟线的研制情况。对该器件的总体结构，电路原理框图、声表面波可程序抽头延迟线结构作了一个扼要的概念。同时分别报道了我所研制的各类声表面波可程序抽头延迟线器件性能指标及相应的图片说明，最后对该器件仍存在的一些问题作了探讨。     

基于CPLD的多路数据采集系统的设计

随着数字化生活的到来,数据采集系统在日常生活中的应用越来越显著。模拟信号和数字信号之间的转换已成为计算机控制系统中不可缺少的环节。较传统数据采集系统,以可编程逻辑器件实现的数据采集系统具有时钟频率高,内部延时小,速度快,效率高,组成形式灵活等特点。