SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

6H-SiC埋沟MOSFET的C-V解析模型研究

研究了6H-SiC埋沟MOSFET器件的电容-电压特性,建立了解析模型.具体分析了埋沟MOSFET各种工作模式下的电容与栅电压之间的关系,考虑了SiO2/SiC界面态及pn结对电容-电压特性的影响.对模型进行了仿真分析验证,结果表明:在假设界面态密度分布均匀条件下,由于对界面态做了简化处理,因而在耗尽模式及夹断模式下的C-V特性计算结果与实验结果有所差异.     

超大规模集成CMOS中PMOS设计的C—V技术

本文介绍了首次提出的一种物理模型.描述经过补偿注入的N阱的C—V曲线.该模型指出,具有Pn给表面的N阱C—V曲线的物理机理与常规C—V曲线完全不同.在高负压区,常数的电容值为栅电容和零偏压pn结电容之串联值;在高正压区,常数的最大电容值为栅电容,P型表面耗尽区电容和极度增大的pn结电容的串联值;在这二个电容值之间,存在一个极小电容值.在较高的补偿注入时,这极小值对应于表面耗尽层接触到pn结空间电荷区;在较低注入时,则对应于表面积累层的开始.不管何种情况,极小值均对应于PMOS的阈值电压且指出表面pn结的形成.应用此种模型,设计了兼有表面型及隐埋型沟道MOS器件优点的超大规模集成CMOS器件.     

用高频C-V特性测量表面势和界面陷阱密度及其分布

本文基于对MOS结构耗尽-弱反型区C-V特性的理论分析,提出了一种利用高频C-V特性直接测量半导体表面势和界面陷阱密度及其按能量分布的简便方法,减少了测量分析的计算量,降低了对样品的要求。本文还给出了一些实验样品的测试结果。     

表面栅静电感应晶体管沿沟道中心线电势分布的解析分析

本文从表面栅静电感应晶体管(SIT)的基本物理模型出发,求出了沿沟道中心线的电势分布和沟道势垒高度的解析表达式.根据所得表达式具体计算了一个典型器件在不同栅源电压V_(GS)和漏源电压V_(DS)下的电势分布和势垒高度.其结果与1978年J.L.Morenza等人对同一器件用计算机数值分析所得的结果吻合较好. 本文给出了该种器件中势垒存在的物理模型,指出了表面栅与隐埋栅器件在势垒形成上的差别:表面栅器件中势垒的形成与源沟n~+n结有关;而隐埋栅器件势垒的形成与源沟n~+n结无关. 本文所得的解析表达式也表明,表面栅结构中势垒的出现需要沟道夹断一定的深度.这与1980年日本J.Ohmi用计算机数值分析所得结论是一致的. 本文所得的势垒高度的解析表达式可以作为进一步求解该种器件各电参数的解析表达式的基础.     

关于“高频MOS-CV分析”实验装置中几个问题的探讨

半导体表面对半导体器件的特性有极大的影响,有时甚至对器件的特性起决定性的作用.半导体器件的可靠性及稳定性在很大程度上决定于半导体表面.所谓C-V分析技术,是指测量并分析MOS电容器的电容一电压特性,以确定氧化层、半导体层及其界面的许多特性.通过对MOS结构C-V特性的测量与分析,可以了解半导体表面的各种状态及SiO_2层中SiO_2-Si界面的各种电荷的性质,测量SiO_2的厚度、硅基体的杂质浓     

非规则半导体器件耗尽区的两维分析

本文提出了应用复变函数的概念,对非规则半导体器件耗尽区进行适当变换,得到了研究非规则反偏pn结区的两维问题的新方法,并应用了自洽的耗尽区逻辑判别,计算了一种实际器件结构,得到了可行的结论.本文为非规则半导体pn结区的两维模拟提供了一种新的途径.     

引入基态施主能级分裂的SiC基MOS电容模型

基态施主能级分裂因素被引入了SiC基MOS电容模型。考虑到能级分裂后,电容C-V特性曲线平带附近的Kink效应,得到有效减弱;并且能级分裂对C-V特性的影响,随掺杂浓度的增加和温度的降低而增强,同时也与杂质能级深度相关。对于耗尽区和弱积累区,由于能级分裂的影响,电容的表面电荷面密度将分别有所增加和降低。     

双极场引晶体管:V.双极电化电流理论（双MOS栅纯基）

本文报告用双极场引晶体管（BiFET）电化电流解析理论计算的内禀结构直流特性,晶体管有两块等同MOS栅,纳米厚度纯硅基,没有产生复合和俘获.用交叉双路或Z形单路递归循环算法,很快得到三个势变量的数字解：静电势,电子和空穴电化学势,从而算出电子和空穴表面和体积沟道电流.三种势边界条件主导地影响内禀结构直流特性,用20个量级跨度电流说明.（10-22-10-2A/□,迁移率400cm^2/（V.s） ,1.5nm厚栅氧化层,30nm厚纯基）强表面沟道内载流子空间电荷限制飘移电流起主导作用,除此以外理论上还观察到,体积沟道物理夹断导致经典飘移电流饱和,因德拜长度（25μm）远大于器件尺寸（25nm） ,纯基内少量电子和空穴载流子屏蔽消失导致纯基内体积沟道完全切断.这种切断是从在1952Shockley结栅场引晶体管理论中描述的非纯基体积沟道物理夹断推理而来.     

6H-SiC氧化层中Na离子的C-V测试研究

半导体热氧化过程中,不可避免会沾污Na离子,造成MOS电容的C-V曲线平带电压漂移.在1200℃下热氧化,生成SiC/SiO2界面,进而制作MOS电容.采用高电压偏置,在高温度条件下作用于MOS电容;利用Keithley590 C-V分析仪,测量其C-V曲线.计算出氧化层Na离子密度为2.26×1012/cm2,高温负高压偏置不能完全恢复MOS电容的C-V特性,且高压偏置处理后的MOS电容在积累区的电容值减小,与Si材料MOS的情况不同.主要原因是SiC氧化层和界面质量较差,在高温和高压下弱键断裂、固定电荷重新分布.     

Low-temperature characterization of buried-channel NMOST

A comprehensive characterization of buried-channel NMOS transistors at low temperatures down to 30 K is reported. The mobilities of both surface (accumulation) and bulk (buried-channel) electrons were determined as a function of surface electric field and gate bias voltage, respectively, at low temperatures. Both surface electron mobility and buried-channel electron mobility increase with decreasing temperatures. However, a peak in the buried-channel electron mobility is observed around 80 K if the neutral region extends to regions of high impurity concentrations near the surface. A modified MOSCAP (Poisson solver) was used to obtain spatial distributions of carriers and to predict the C-V curves. Low-frequency noise measurements at low temperatures were carried out at gate voltages corresponding to the accumulation, depletion, and inversion modes of operation of the device. In the accumulation mode, a 1/f dependence is observed similar to surface-channel devices. In the depletion mode, a generation-recombination type of noise is observed with a peak around 150 K. In the inversion mode, noise that is related to the hole inversion layer is observed     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

4H-SiC p-i-n紫外光电探测器的电容-电压特性研究

分析并比较了4H-SiC p-i-n紫外光电探测器的电容-电压（C-V）特性随温度和偏置电压的变化情况,观测到4H-SiC p-i-n结构中的深能级缺陷。结果表明：由于近零偏压时探测器i型层已处于耗尽状态,其高频（1 MHz）C-V特性几乎不随反向偏压变化,随着温度升高,被热离化的自由载流子数量增多导致高频结电容随之增大;探测器的低频（100 kHz）结电容比高频结电容具有更强的电压和温度依赖性,原因在于被深能级缺陷俘获的载流子随反向偏压增大或随温度升高而被离化,从而对结电容产生影响。     

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.     

Application of junction capacitance measurements to the characterization of solar cells

The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.     

A model for the capacitance—Voltage characteristics of MODFET's

Using Fermi-Dirac statistics, a model for the gate capacitance-voltage characteristics of MODFET's is developed that includes not only the capacitance component due to two-dimensional electron gas density but also the capacitance component due to donor neutralization. To analytically solve Poisson's equation with the Fermi-Dirac statistics, we analyzed the theory by using two regions (the complete ionization region and the partial ionization region of doped impurities). Using the obtained C-V relationships, the gate capacitance is calculated with the numerical calculation method. The results are in good agreement with experimental data.     

Gate field emission induced breakdown in power SiC MESFETs

The breakdown mechanism of SiC MESFETs has been analyzed by careful investigation of gate leakage current characteristics. It is proposed that gate current-induced avalanche breakdown, rather than drain avalanche breakdown, is the dominant failure mechanism for SiC MESFETs: thermionic-field emission and field emission are dominant for the ON state (above pinch-off voltage) and the OFF state (below pinch-off voltage), respectively. The effect of Si/sub 3/N/sub 4/ passivation on breakdown voltage has been also investigated. Si/sub 3/N/sub 4/ passivation decreases the breakdown voltage due to higher electric field at the gate edge compared to edge fields before passivation. A reduction in surface trapping effects after passivation results in the higher electric field because the depletion region formed by trapped electrons is reduced significantly.     

S-band operation of SiC power MESFET with 20 W (4.4 W/mm) output power and 60% PAE

Previous efforts have revealed instabilities in standard SiC MESFET device electrical characteristics, which have been attributed to charged surface states. This work describes the use of an undoped "spacer" layer on top of a SiC MESFET to form a "buried-channel" structure where the active current carrying channel is removed from the surface. By using this approach, the induced surface traps are physically removed from the channel region, such that the depletion depth caused by the unneutralized surface states cannot reach the conductive channel. This results in minimal RF dispersion ("gate lag") and, thus, improved RF performance. Furthermore, the buried-channel approach provides for a relatively broad and uniform transconductance (G/sub m/) with gate bias (V/sub gs/), resulting in higher efficiency MESFETs with improved linearity and lower signal distortion. SiC MESFETs having 4.8-mm gate periphery were fabricated using this buried-channel structure and were measured to have an output power of 21 W (P/sub out//spl sim/4.4 W/mm), 62% power added efficiency, and 10.6 dB power gain at 3 GHz under pulse operation. When operated at continuous wave, similar 4.8-mm gate periphery SiC MESFETs produced 9.2 W output power (P/sub out//spl sim/2 W/mm), 40% PAE, and /spl sim/7 dB associated gain at 3 GHz.     

Measurement of the mobility and concentration of carriers in diffused zones in Si with a gate controlled structure

A gate controlled structure is described. It is shown to be a convenient device for measuring mobility and concentration profile of majority carriers in diffused zones. The values of these two parameters are derived from measurements of gate capacitance and resistivity as a function of gate voltage. Various ways of obtaining C-V deep-depletion curves are discussed in order to justify the choice of a gate controlled structure. The measurement technique is discussed. Limitations of the method are due, on one hand, to the depletion approximation and, on the other hand, to an excessive reverse current across the diffused junction induced by the gate voltage. This effect is encountered especially in low-concentration samples, such as ours, in the range of 10¹⁵-10¹⁶cm^-3. For illustration purposes, profiles of a p diffusion used in the MOSC process are measured at the beginning and at the end of the fabrication process.