共查询到19条相似文献，搜索用时 31 毫秒
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从自洽求解二维泊松方程和薛定谔方程出发,研究了纵、横向电场作用下GaNHFET沟道中的电子态和夹断特性。建立了不同异质结构和电场梯度下的电荷控制模型;运用热电子隧穿电流崩塌模型解释了强场电流崩塌的实验结果;强调了沟道夹断特性对电流崩塌的影响;研究了背势垒异质结构、场板电极和挖槽等抑制电流崩塌的方案,提出利用挖槽独立设计内、外沟道异质结构抑制强场电流崩塌的新思路。 相似文献
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掺HCI栅氧化对MOS结构电特性的影响 总被引：1，自引：0，他引：1
研究了栅氧化时掺ＨＣｌ的硅栅ＭＯＳＦＥＴ的ＤＤＳ－ＶＧＳ特性，阈电压和界面态。结果发现，ＨＣｌ掺入栅介质，可使ＩＤＳ－ＶＧＳ曲线正向漂移，ＰＭＯＳＦＥＴ阈电压绝对值减小，ＮＭＯＳＦＥＴ阈电压增大，Ｓｉ／ＳｉＯ２界面态密度下降，采用氯的负电中心和Ｓｉ／ＳｉＯ２界面硅悬挂键的键合模型对实验结果进行了解释。 相似文献
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基态施主能级分裂因素被引入了SiC基MOS电容模型。考虑到能级分裂后,电容C-V特性曲线平带附近的Kink效应,得到有效减弱;并且能级分裂对C-V特性的影响,随掺杂浓度的增加和温度的降低而增强,同时也与杂质能级深度相关。对于耗尽区和弱积累区,由于能级分裂的影响,电容的表面电荷面密度将分别有所增加和降低。 相似文献
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提出了一种SiC隐埋沟道MOSFET平均迁移率模型,并在此基础上对器件I-V特性进行了研究。采用一个随栅压变化的平均电容公式,并用一个简单的解析表达式来描述沟道平均迁移率随栅压的变化关系。计算漏电流时考虑了埋沟器件的三种工作模式,推出了各种工作模式下的漏电流表达式,并用实验值对模型进行了验证。 相似文献
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A novel approach for the fabrication of a metal oxide semiconductor(MOS) structure was reported.The process comprises electrochemical deposition of aluminum and zinc layers on a base of nickel-chromium alloy. This two-layer structure was thermally oxidized at 400℃for 40 min to produce thin layers of aluminum oxide as an insulator and zinc oxide as a semiconductor on a metallic substrate.Using deposition parameters,device dimensions and SEM micrographs of the layers,the device parameters were calculated.The resultant MOS structure was characterized by a C-V curve method.From this curve,the device maximum capacitance and threshold voltage were estimated to be about 0.74 nF and -2.9 V,respectively,which are in the order of model-based calculations. 相似文献
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This paper investigates the capacitance-voltage （C-V） measurement on fully silicided （FUSI） gated metal-oxide-semiconductor （MOS） capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the threeelement and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor＇s area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation ha 相似文献
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This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface. 相似文献
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A novel approach for the fabrication of a metal oxide semiconductor(MOS) structure was reported.The process comprises electrochemical deposition of aluminum and zinc layers on a base of nickel-chromium alloy. This two-layer structure was thermally oxidized at 400℃for 40 min to produce thin layers of aluminum oxide as an insulator and zinc oxide as a semiconductor on a metallic substrate.Using deposition parameters,device dimensions and SEM micrographs of the layers,the device parameters were calculated.T... 相似文献
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在考虑到杂质的不完全离化作用时,建立了S iC埋沟PM O SFET在发生表面多子耗尽时的电流解析模型。实验结果和模拟结果的一致性说明了此模型的准确性。在300~600 K温度范围表面弱电场的条件下,由于杂质不完全离化作用得到充分体现,因此器件的工作状态有不同于常规模型下的特性;当温度升高时离化率的增大使得杂质的不完全离化作用得不到体现,所以文中模型的结果向常规模型的结果靠近,且都与实验结果接近。同时为了充分利用埋沟器件体内沟道的优势,对埋沟掺杂的浓度和深度也进行了合理的设计。 相似文献