Structural and magnetic properties of silver doped melt-textured YBCO prepared in a solar furnace

Magnetic measurements and structural investigation have been performed on melt-textured YBCO and AgYBCO HTS. The “sun” technique produces very dense YBCO (ρ=5.86 g cm⁻³) and AgYBCO [ρ=6.36 g cm⁻³; 10% b/w (by weight) silver. This technique renders samples with a large volume fraction of the Y₂BaCuO₅ (211) phase. The material is characterized by very high J_c values, as compared with bulk polycrystalline YBCO prepared by other methods. This feature is attributed to the enhanced amount of 211 particles which serve as pinning centers. Additional significant densification of the structure due to silver incorporation is obtained, and a reduction of the size of 211 inclusions is also observed. Silver doped samples show “butterfly”-like hysteresis loops at relatively high temperatures (T≥60K). This feature is probably associated with oxygen deficiency which arises from the slower oxygen diffusion into silver doped samples. J_c values enhancement was obtained in silver doped “sun” samples at high temperatures (T≥60K) and fields of 20–30 kOe. The temperature dependence of effective activation energy of pinning, U_eff, was measured for YBCO and AgYBCO materials. U_eff is higher in silver doped samples in the high temperature region T≥60K.     

Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77 K to 300 K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μ_e) and hole (μ_h) mobilities, both at about 1.6 cm²/V s. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μ_e indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μ_e and μ_h both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230 K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T < 210 K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.     

Effect of magnetic field on galvanomagnetic properties of mica/Bi/EuS heterostructures

The dependences of the Hall coefficient R_H and magnetoresistance Δρ/ρ on magnetic field (B=0.01?1.0 T) were obtained in the temperature range 77–300 K for thin Bi films with thicknesses d=40–250 nm, grown on mica substrates and covered by a EuS layer. It was established that in the entire temperature range for all Bi films the criterion of weak field was fulfilled at magnetic fields up to 1 T: R_H remained practically constant in the entire range of magnetic field and Δρ/ρ for all investigated samples changed with changing magnetic field according to a parabolic law.     

Study of the correlation between structural and photoluminescence properties of CdSe thin films deposited by close-spaced vacuum sublimation

CdSe polycrystalline films were deposited by a close-spaced vacuum sublimation method at different substrate temperatures (T_s) using glass slides as substrates. At T_s≤673 K the films have a structure with strong dispersion of grain size (d) (from 0.1 to 0.3 μm). In this case the layer-by-layer mechanism determines the growth process of the layers. For T_s=873 K they have a columnar-like structure with a clear growth texture and the average grain size d=3–4 μm. The films obtained at T_s>473 K are n-type and only correspond to a single wurtzite phase. The crystallites are preferentially oriented with the (102) planes parallel to the substrate. At lower temperatures the films are bi-phase. The microstress level in CdSe films obtained at Т_s=873 K (0.5×10⁻³) is considerably smaller than for the films deposited at Т_s=773 K (4.0×10⁻³). Increase of the value of T_s improves the stoichiometry of CdSe films. Analysis of the low-temperature photoluminescence (PL) spectra let us determine the nature and energy of point and extended defects in the investigated films. It was shown that the films contain Na(Li) and P residual impurities. The results of the structural and PL measurements showed that the CdSe polycrystalline films are of fairly good crystal and optical quality for T_s=873 K and can be suitable for various applications.     

Scaling limits of organic digital circuits

The effect of device scaling on organic circuits’ performance was studied. Particularly, the influence of contact resistance on the static and the dynamic behavior of the circuits was investigated. For that purpose, an analytical model describing the voltage transfer characteristics (VTCs) and the propagation delay was developed. Using the model, it was shown that for OTFTs with channel lengths of less than 10 μm the contact resistance has negative influence on both, the static noise margin (SNM) and the propagation delay. Moreover, the model is in a good agreement with experimentally measured data. Scaling the lateral dimensions of the transistors down to few μm limits the circuit performance due to contact effects, and the 1–10 MHz frequency range operation required by some applications can only be achieved by reducing the specific contact resistance, ρ_c, 10–100 times. This need for ρ_c reduction highlights the importance of improving charge injection in organic transistors that can usually be achieved by contact doping like in inorganic electronics.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (R_g) resulting in the better microwave performance. By increasing the length of field-plate metal extension (L_FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (I_ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L_FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L_FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors

The temperature dependence in the typical temperature operating range from 300 K up to 370 K of the electrical characteristics of IGZO TFTs fabricated at temperatures not exceeding 200 °C is presented and modeled.It is seen that up to T = 330 K, the transfer curves show a parallel shift toward more negative voltages. In both subthreshold and above threshold regimes, the drain current shows Arrhenius-type dependence. In the latter case, for low temperatures, the activation energy is around 0.35 eV for V_GS = 10 V, reducing as V_GS is increased. The observed behavior is consistent with having the VRH transport mechanism as the predominant one in conduction.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Microbridge preparation through spincoating and photolithography without etching

It is possible to produce HTSC thin films of polymer metal precursors by the simple spincoating technique. This method can be used to manufacture of Y–Ba–Cu–O- and Bi–Sr–Ca–Cu–O–HTSC thin films. The microbridges are generated into the precursor film by photolithography. The etching process step is cancelled. After that the superconducting phases are formed at 950°C respectively 865°C during the tempering process. The HTSC structures serve as a previous stage for SNS contact. The critical temperatures (T_c) measured on the 20 and 200 μm wide microbridges are 82 K for Y–Ba–Cu–O and 108 K for Bi–Sr–Ca–Cu–O. The critical current density (j_c) obtained is 10⁵ A/cm² for 65 K.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Improvement in negative differential conductance characteristics of hole resonant-tunneling diodes with high Ge fraction Si/strained Si1−xGex/Si(1 0 0) heterostructure

Hole resonant-tunneling diodes (RTD) with Si/strained Si_1?xGe_x heterostructures epitaxially grown on Si(1 0 0) have been fabricated and improvement in negative differential conductance (NDC) characteristics for high Ge fraction such as x = 0.5 was investigated. It is clearly shown that SiH₄ exposure at low temperatures of 400–450 °C just after Si_1?xGe_x epitaxial growth is effective to suppress surface roughness in atomic order. In the case of the RTD with x = 0.48, NDC characteristics for 1.4-nm thick Si barriers were observed at higher temperatures around 270 K than that for 2.4-nm thick Si barriers. By increasing the Ge fraction to x = 0.58, NDC characteristics were also observed at higher temperatures around 290 K than that with x = 0.48.     

Effect of Fe doping on structural and magnetic properties of La2/3Ca1/3Mn1−yFeyO3 (y=0–0.03) thin films

We have characterized the magnetic and structural properties of pure and ⁵⁷Fe-doped La_2/3Ca_1/3MnO₃ thin films and targets, substituted with 1% and 3% of ⁵⁷Fe on the Mn site. The films were prepared via high O₂-pressure (500 mTorr) by DC magnetron sputtering on (1 0 0) SrTiO₃ and (1 0 0) LaAlO₃ single-crystal substrates. Mössbauer spectra measured at room temperature confirm the presence of Fe³⁺ with octahedral coordination, thus indicating that Fe is incorporated into the structure by substituting Mn. Structural analysis by X-ray diffraction (XRD) shows that the films are single phase and c-axis oriented and that the Fe doping gives rise to a relaxation of the epitaxial strain. Interestingly, the Curie temperature and the magnetoresistance (MR) show a non-monotonic behavior with Fe doping. This indicates that initially the strain relaxation induced by the Fe doping is more important than the reduction of ferromagnetic coupling due to the Fe incorporation.     

Muon-spin-relaxation study of organic semiconductor spiro-linked compound

We report on muon-spin-relaxation (μSR) experiment of organic semiconductor spiro-linked compound 2′,7′-bis(N,N–diphenylamino)-2-(5-(4–tert-butylphenyl)-1,3,4-oxadiazol-2-yl)-9,9-spirobifluorene (Spiro-DPO) measured at temperatures between 8 and 300 K and at longitudinal fields up to 395 mT in order to study charge transport properties in organic semiconductor. The μSR time spectra were analyzed by using Risch and Kehr (RK) function and it indicates a transition from one-dimensional hopping transport of charge carriers at low temperatures to two- or three-dimensional hopping transport at high temperatures (>75 K).     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Long lengths of silver-clad Bi2223 superconducting tapes with high current-carrying capacity

Long lengths of silver-clad (Bi,Pb)₂Sr₂Ca₂Cu₃O₁₀ (Bi2223) high-T_c multifilamentary tapes were produced using the powder-in-tube (PIT) technique followed by a thermomechanical process. The relationships between microstructure and electrical, magnetic and mechanical properties of the heat treated tape were evaluated from the critical current density measurements, irreversibility magnetic field determination and mechanical bending tests. Emphasis was stressed on the J_c behavior in magnetic fields at different temperatures. A J_c of 10,000 A/cm² at 77 K in a zero field for a 10 m tape and 75,000 A/cm² at 23 K in a field of 3 T for a short tape was achieved. The results obtained showed that Bi2223/Ag high-T_c composite tapes are a potential alternative to conventional low-T_c superconductors in magnetic levitation (MAGLEV) applications.     

Biaxially aligned YBCO film tapes fabricated by all pulsed laser deposition

Biaxially aligned yttria-stabilized zirconia (YSZ) films on Ni-based alloy substrates were realized with high deposition rate of 0.5 μm min⁻¹ by the inclined substrate deposition (ISD) technique without ion beam assistance. The microstructure of YSZ was examined to study the growth mechanism of biaxial alignment by ISD. Columnar structures toward the plasma plume suggested a self-shadowing effect in the ISD process. To raise I_c values, YBCO thickness was increased up to 5 μm. Thick YBCO films with high J_c values were realized on the ISD-grown YSZ. Long YBCO tapes with biaxial alignment were successfully fabricated using continuous pulsed laser deposition and a high I_c value of 37.0 A (77.3 K, 0 T) at a 75 cm voltage tap spacing was achieved.