长飞少模光纤分析

阐述光纤通信的发展现状,分别介绍长飞低串扰少模光纤、长飞低群差分时延少模光纤、长飞低衰减少模光纤、长飞Ring-core少模光纤4种少模光纤的特点,并对空分复用技术的发展提出建议.     

浅谈正交频分复用技术及其应用

本文简要叙述了正交频分复用技术的基本原理和优势,并结语了正交频分复用技术在实际生活中的应用,最后阐述了正交频分复用技术的不足之处并展望了未来的发展前景。     

正交频分复用技术及其在CDMA中的应用

主要介绍正交频分复用技术的基本原理和多载波ＣＤＭＡ技术的实现方法，并简要讨论了正交频分复用技术相对于多载波ＣＤＭＡ技术的优缺点。     

光纤通信新型复用技术(本期优秀论文)

介绍了基于少模光纤(FMF)的MDM技术和基于涡旋光纤的OAM复用技术的研究背景与最新研究进展,并对其原理和理论模型进行概述,讨论了OAM模式的生成方式、OAM复用技术和模分复用的特点,并对这两种技术面临问题的解决方法和复用技术的发展方向提出了一些思路。     

基于广播地面的分层复用系统研究

介绍了基于地面广播的层分复用(Layered Division Multiplexing,LDM)技术的研究与进展.采用层分复用技术可以在不同的接收环境下根据应用需求来选择不同的功率和不同的编码调制方式,能极大地提高频谱的利用率和使用灵活性,且可应用于多个不同的系统中.正是由于该技术的以上特点,层分复用技术被ATSC3.0的专家组选为下一代ATSC3.0标准物理层的核心技术之一,同时被2015年美国广播电视协会展选为最佳技术.首先介绍层分复用技术的初始思想——“云传输”的基本概念,进一步从层分复用系统框架方面,着重介绍层分复用技术在噪声与层间干扰处理、帧结构设计、发射识别和信号消除等方面的设计方法,最后对层分复用技术为地面广播系统带来的性能提升进行了总结.     

群延时谱参数在汉语数字语音识别中的应用

汉语数字语音之间的高混淆性直接影响了汉语数字语音识别的效果，传统的语音识别方法很难对易混淆的语音做出有效的区分。本文提出了一种多参数、多级识别策略，先采用MEL谱参数基于HMM进行初级数字语音识别，然后对易混淆的数字对采用一种新的群延时谱参数——RRCGD-CC(Reflected Roots Chirp Group Delay-Cepstral Coefficients)基于SVM进行二次分类。实验结果表明，通过多参数多级识别方法，数字“2”和“8”的识别率提高了8%，数字识别系统的整体识别率提高了2.3%。这一结果充分说明了本文提出的多参数多级识别方法有利于提高汉语数字语音识别系统的识别性能，同时也说明了RRCGD-CC在易混淆数字语音的识别上是有效的。      

HIPERLAN/2中正交频分复用技术仿真性能研究

讨论HIPERLAN／2标准的物理层结构，分析HIPERLAN／2中正交频分复用技术特点，提出正交频分复用系统仿真模型，并对不同的数字调制方式及编码效率的正交频分复用系统进行研究，给出系统传输的误码率性能。     

基于正交频分复用的水声通信系统

由于海洋的恶劣传输条件,实现可靠的水声通信是对通信和信号处理技术的挑战,正交频分复用技术由于具有其独特的优势得到了广泛的应用。介绍了基于正交频分复用技术的水声通信系统组成结构,并进行分析。给出了水声信道模型,对正交频分复用的关键技术进行描述。结合水声信道的特性,提出一种频偏估计及补偿方法。     

漫谈各种复用技术

本介绍了各种复用技术．包括频分复用、时分复用和码分复用等．指出了各种复用技术的应用。     

新一代宽带城域网技术的应用与比较

随着骨干传输网、局域网容量的大幅度增长，网络宽带化的“瓶颈”已经转移到了城域网。文中分别介绍当前城域网中的粗波分复用技术、10G以太网技术和弹性分组环技术，并对其特点和应用作了分析比较，最后提出了构建新一代城域网的基本思路。     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

A Novel Simple Semi-Empirical Model for the Effective Earth Radius Factor

This paper presents a dual cumulative probability distribution model for predicting the cumulative distribution of the probability that a particular value of the propagation k-factor will be exceeded. The distributions relate to so-called "dry" and "wet" (or "climatic") components. The model is based on meteorological radiosonde data observed over a period of some 11 years and published by other workers. The model is extended by a simple height regression analysis in order to predict the cumulative behavior of the k-factor at different ground level heights in the summer rainfall area of South Africa during different months. Comparisons are made between predicted and observed data. The model may have potential applications in other parts of the world where data on k-factor behavior are scarce     

截面数据重构三角网格面算法的研究

截面数据是逆向工程中常见的曲面重构数据来源。采用相邻轮廓线间添加剖分线段的方法实现三角网格面的生成,并且在传统算法基础上,加入了“缓剖分”和“错位修正”等策略,使所述算法在输出结果的准确性方面得到了大幅提升。     

耦合目标近场散射外推技术研究

针对具有多次散射的耦合目标在不满足远场条件下测量的散射方向图发生畸变的问题,通过分析耦合目标的近场-远场转换关系,提出一种"多发多收"模式的近场散射外推方法.在获得全角域的近场双站信息后,对各角度近场接收的散射数据进行外推处理,然后根据互易定理,将外推后的数据等效为"远场发射、近场接收"数据.接下来对该数据再进行一次外推,满足"远场发射、远场接收"的条件,最后取出对角线上的元素获得各角度的远场RCS（Radar Cross Section,RCS）.通过建立存在强耦合机制的二面角和腔体结构模型,利用FEKO和MATLAB软件对方法进行仿真,将"多发多收"外推的结果与远场RCS进行比对.结果表明：该方法得到的结果与远场RCS方向图吻合良好,全角域均值误差小于1dB,验证了方法的有效性.     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

采集数据无效值的剔除方法

计算机处理过的数据，往往有些误差太大。如果数据比较多，人工剔除比较麻烦。但如果用数组读出相关数据，再通过数组进行计算和剔除，这样既不会破坏原数据，又对数据做了比较好的处理。通过对二维激光测速仪、爆破振动参数采集仪IDTS测试产生的数据结果做必要的坏值剔除，实现了较满意的结果。     

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

Recursive linear smoothing of two-dimensional random fields

In an earlier paper, recursive formulas for the causal filtering of two-dimensional random fields were developed. "Causality" in two dimensions is not a physical constraint but rather an artifact introduced to generate recursion, which in turn is motivated by computational efficiency. The earlier results are extended here in order to derive some recursive formulas for "smoothing" estimators which use all the data rather than just the data in the "past".     

基于FPGA的图像采集模块的设计

针对传统的PCI图像采集卡的弊端,采用OV7620和Cyclone系列FPGA设计了适用于便携式嵌入式系统的图像采集模块。该模块采用“乒乓模式”设计思想,具有8Mbit的高速缓存空间,并利用嵌入式逻辑分析仪对原始图像数据的采集和缓存。系统实现图像原始数据的采集和缓存,保证图像数据的连续和完整性,该系统外部接口电路简单,便于使用和移植,具有体积小、功耗低、速度快等优点,可应用于便携式设备的图像采集。