A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

Gaussian distribution of inhomogeneous barrier height in tungsten/4H-SiC (000-1) Schottky diodes

The Gaussian distribution model have been used to analyze the anomalies observed in tungsten (W)/4H-SiC current voltage characteristics due to the barrier inhomogeneities that prevail at the metal-semiconductor interface. From the analysis of the forward I-V characteristics measured at elevated temperatures within the range of 303-448 K and by the assumption of a Gaussian distribution (GD) of barrier heights (BHs), a mean barrier height of 1.277 eV, a zero-bias standard deviation σ₀ = 0.092 V and a factor T₀ of 21.69 K have been obtained. Furthermore the modified Richardson plot according to the Gaussian distribution model resulted in a mean barrier height and a Richardson constant (A^∗) of 1.276 eV and 145 A/cm² K², respectively. The A^∗ value obtained from this plot is in very close agreement with the theoretical value of 146 A/cm² K² for n-type 4H-SiC. Therefore, it has been concluded that the temperature dependence of the forward I-V characteristics of the W/4H-SiC contacts can be successfully explained on the basis of a thermionic emission conduction mechanism with Gaussian distributed barriers. In addition, a comparison is made between the present results and those obtained previously assuming the pinch-off model.     

Barrier characteristics of gold Schottky contacts on moderately doped n-InP based on temperature dependent I-V and C-V measurements

The temperature dependences of current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the gold Schottky contacts on moderately doped n-InP (Au/MD n-InP) Schottky barrier diodes (SBDs) have been systematically investigated in the temperature range of 60-300 K. The main diode parameters, ideality factor (n) and zero-bias barrier height (apparent barrier height) were found to be strongly temperature dependent and while the decreases, the n and the increase with decreasing temperature. According to Thermionic Emission (TE) theory, the slope of the conventional Richardson plot [In(J₀/T²) vs. 1000/T] should give the barrier height. However, the experimental data obtained do not correlate well with a straight line below 160 K. This behaviour has been interpreted on the basis of standard TE theory and the assumption of a Gaussian distribution of the barrier heights due to barrier inhomogeneities that persist at the metal-semiconductor interface. The linearity of the apparent barrier height vs. 1/(2kT) plot that yields a mean barrier height of 0.526 eV and a standard deviation (σ_s0) of 0.06 eV, was interpreted as an evidence to apply the Gaussian distribution of the barrier height. Furthermore, modified Richardson plot [ vs. 1/T] has a good linearity over the investigated temperature range and gives the and the Richardson constant (A^∗) values as 0.532 eV and 15.90 AK⁻²cm⁻², respectively. The mean barrier heights obtained from both plots are appropriate with each other and the value of A^∗ obtained from the modified Richardson plot is close to the theoretical value of 9.4 AK⁻²cm⁻² for n-InP. From the C-V characteristics, measured at 1 MHz, the capacitance was determined to increase with increasing temperature. C-V measurements have resulted in higher barrier heights than those obtained from I-V measurements. The discrepancy between Schottky barrier heights(SBHs) obtained from I-V and C-V measurements was also interpreted. As a result, it can be concluded that the temperature dependent characteristic parameters for Au/MD n-InP SBDs can be successfully explained on the basis of TE mechanism with Gaussian distribution of the barrier heights.     

A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants

This paper proposes a novel structure of ASK (amplitude shift keying) demodulators, which requires no external capacitors, for implantable micro-stimulators. By using a traditional β multiplier reference to detect the signal envelope, followed by a Schmitt trigger and a load driver, the large off-chip capacitor in traditional ASK demodulators is not required any more. Therefore, the proposed circuit possesses small area to be integrated in an SOC (system-on-chip). Besides, due to the lack of the large capacitor, the proposed circuit can operate with a higher data rate using lower frequency carriers. The proposed circuit is integrated in an implantable micro-stimulator on silicon using 2P4M CMOS process. The area of the proposed circuit occupies merely with a maximum power dissipation of less than 12 mW (including the power consumption of the analog circuits of the micro-stimulator) by measurement results on silicon. Moreover, the measurement results verify that the proposed ASK demodulator can detect the ASK modulated signal up to 570 kbps data rate at 2 MHz carrier frequency when the modulation index is 10%.     

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF_min of 4.46 dB. The reverse isolation S12 of the LNA can achieve and the input and output return losses are better than . The input 1-dB compression point is and IIP3 is . This LNA drains 10 mA from the supply voltage of 1 V.     

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

A novel nonvolatile memory based on self-organized quantum dots

A novel type of memory based on self-organized quantum dots (QDs) is presented, which merges the advantages of the most important semiconductor memories, the dynamic random access memory (DRAM) and the Flash. A nonvolatile memory with fast access times and good endurance (>10¹⁵ write/erase cycles) as an ultimate solution seems possible. A storage time of 1.6 s at 300 K in InAs/GaAs QDs with an additional Al_0.9Ga_0.1As barrier is demonstrated and a retention time of 10⁶ years is predicted for GaSb QDs in an AlAs matrix. A minimum write time of 6 ns is obtained for InAs/GaAs QDs. This value is already in the order of the access time of a DRAM cell and at the moment limited by the RC low pass of the device. An erase time of milliseconds is shown in first measurements on GaSb/GaAs QDs at . Faster write/erase times below even at room temperature are expected for improved device structures.     

Current transport mechanisms and trap state investigations in (Ni/Au)-AlN/GaN Schottky barrier diodes

The current transport mechanisms in (Ni/Au)-AlN/GaN Schottky barrier diodes (SBDs) were investigated by the use of current-voltage characteristics in the temperature range of 80-380 K. In order to determine the true current transport mechanisms for (Ni/Au)-AlN/GaN SBDs, by taking the J_s(tunnel), E₀, and R_s as adjustable fit parameters, the experimental J-V data were fitted to the analytical expressions given for the current transport mechanisms in a wide range of applied biases and at different temperatures. Fitting results show the weak temperature dependent behavior in the saturation current and the temperature independent behavior of the tunneling parameters in this temperature range. Therefore, it has been concluded that the mechanism of charge transport in (Ni/Au)-AlN/GaN SBDs, along the dislocations intersecting the space charge region, is performed by tunneling.In addition, in order to analyze the trapping effects in (Ni/Au)-AlN/GaN SBDs, the capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics were measured in the frequency range 0.7-50 kHz. A detailed analysis of the frequency-dependent capacitance and conductance data was performed, assuming the models in which traps are located at the heterojunction interface. The density (D_t) and time constants (τ_t) of the trap states have been determined as a function of energy separation from the conduction-band edge (E_c − E_t) as D_t≅(5-8)×10¹², respectively.     

Self-aligned In0.49Ga0.51P/GaAs HBT DC and RF characteristics related with orientations

A self-aligned InGaP/GaAs HBT DC and RF characteristics related with orientations were studied. The DC current gain was greater for the [0 1 1] emitter orientation compared to orientation. However, it also showed slightly better RF performance for orientation with a cutoff frequency f_T 69 GHz compared to the f_T of 62 GHz for the [0 1 1] orientation. This experimental work has been proposed that the dependence of the characteristics could be attributed to both piezoelectric effect and the difference between lateral etched profiles in different directions.     

High-speed CMOS unity-gain current amplifier

A high-performance CMOS unity-gain current amplifier is proposed. The solution adopts two feedback loops to reduce the input resistance and a nested-Miller technique to provide frequency compensation. A design example using a 0.8 μm process and a 2 V supply is given and SPICE simulations show a bandwidth of 75 MHz, no slew-rate limitations and a settling time better than 50 ns, irrespective of the current amplitude. Input and output resistances are better than 0.1 Ω and 15 MΩ, respectively. The input-referred white noise spectral density is .     

YBCO superconducting tapes by melt-annealing method on metallic Ni%5W substrates

Superconducting tapes of YBCO-123 were produced by melt-annealing method on metallic Ni%5W substrates. YBCO thick films of about thick were deposited on Ni%5W tapes previously CeO₂ coated using different thermal treatments. A final architecture of the tapes like Ni%5W/CeO₂/YBCO/Au-Pd was achieved.Critical temperatures (T_c) of the superconducting tapes around 89 K and critical current densities (J_c) of at 77 K and were determined by resistive methods. All the samples displayed a granular character and the crystalline structure of the superconducting YBCO-123 with and preferential orientation along the c-axis as determined by SEM and XRD analysis, respectively. Both grain sizes and c-axis orientation are dependent of the thermal treatments.     

Occurrence of ferroelectricity in epitaxial BiMnO3 thin films

In this paper, we report evidence of ferroelectricity in perovskite manganite (BiMnO₃) thin films synthesized via r.f. magnetron sputtering method on a single-crystal (1 0 0)-oriented SrTiO₃:Nb 0.1% and Pt/TiO₂/SiO₂/Si substrates. X-ray diffraction measurements were used to analyse the crystal structure of the thin films, revealing epitaxial growth for BiMnO₃ films with their (1 1 1) and (2 2 2) planes parallel to the (0 0 1) and (0 0 2) planes of the SrTiO₃ substrate. AFM measurements were performed to investigate surface morphology; quantitative values of roughness and grain size are in the range between 300 and 500 nm. Ferroelectric characterization was conducted at low temperatures and at 300 K. Hysteresis loops (polarization vs. voltage) were obtained, showing saturation polarizations of , and at 105, 122, and 300 K. Resistance vs. temperature measurements were performed, which indicated this to be very robust insulating material.     

A CMOS image sensor with light-controlled oscillating pixels for an investigative optobionic retinal prosthesis system

This paper presents a high-dynamic range CMOS image sensor architecture incorporating light-controlled oscillating pixels which can act as front-end for an investigative optobionic retinal prosthesis research effort. Each pixel acts as an independent oscillator, whose frequency is proportional to the local light intensity. A 9×9 pixel array has been fabricated in the AMS CMOS opto process. Each pixel's area amounts to , each pixel photodiode area is while the array occupies . Measured results show that the sensor can achieve a linear optical dynamic range of 80 dB (from 0.24 Hz to 2.2 kHz). Its linear electrical dynamic range exceeds 134 dB (from 100 mHz to 502 kHz). The nominal power dissipation is about 50 nW per pixel.