共查询到18条相似文献,搜索用时 187 毫秒
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1.25 Gbps并串转换CMOS集成电路 总被引:2,自引:0,他引:2
分析了由超高速易重用单元构造的树型和串行组合结构 ,实现了在输入半速率时钟条件下 1 0路到1路吉比特率并串转换。通过理论推导着重讨论了器件延时和时钟畸变对并串转换的影响 ,指出了解决途径。芯片基于 0 .3 5μm CMOS工艺 ,采用全定制设计 ,芯片面积为 2 4.1 9mm2 。串行数据输出的最高工作速率达到 1 .62 Gbps,可满足不同吉比特率通信系统的要求。在 1 .2 5 Gbps标准速率 ,工作电压 3 .3 V,负载为 5 0 Ω的条件下 ,功耗为 1 74.84m W,输出电压峰 -峰值可达到 2 .42 V,占空比为 49% ,抖动为 3 5 ps rms。测试结果和模拟结果一致 ,表明所设计的电路结构在性能、速度、功耗和面积优化方面的先进性。文中设计的芯片具有广泛应用和产业化前景。 相似文献
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介绍了可用于SDH STM-64光纤传输系统的4∶1复接器.整个电路采用树型结构,低速的复接单元采用动态双相伪NMOS逻辑实现,高速的复接单元采用SCL逻辑实现,提出了一种新型采用正反馈对的单端转双端电路,实现由低速单元到高速单元的逻辑变换.基于此结构的全定制单片集成电路采用0.18 μm CMOS工艺设计并实现.测试结果表明,在供电电压1.8 V,50 Ω负载条件下,复接输出数据速率超过10 Gbit/s,在标准速率10 Gbit/s,输出电压峰-峰值180 mV时,功耗仅为180mW,抖动4.9/s(rms),芯片面积为0.89 mm2×0.7 mm2. 相似文献
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采用CSMC0.6μm CMOS工艺设计实现了速率为622Mbps的4∶1复接器和激光二极管驱动器电路。4∶1复接器采用树型结构,由3个2∶1复接器组成。激光二极管驱动器电路由两级差分放大器和一级电流开关构成,级间采用源级跟随器隔离。电路芯片尺寸为1.5mm×0.7mm。电路采用单一正5V电压供电,功耗约为900mW。测试结果表明,电路的最高工作速率超过1.25Gbps速率,输出最大电流超过85mA。 相似文献
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介绍了可用于SDHSTM-64光纤传输系统的4:1复接器.整个电路采用树型结构,低速的复接单元采用动态双相伪NMOS逻辑实现,高速的复接单元采用SCL逻辑实现,提出了一种新型采用正反馈对的单端转双端电路,实现由低速单元到高速单元的逻辑变换.基于此结构的全定制单片集成电路采用0.18μm CMOS工艺设计并实现.测试结果表明,在供电电压1.8V,50Q负载条件下,复接输出数据速率超过10Gbit/s,在标准速率10Gbit/s,输出电压峰一峰值180mV时,功耗仅为180mw,抖动4.9/s(rms),芯片面积为0.89mm^2×0. 7 mm^2. 相似文献
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This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process. 相似文献
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基于1μm GaAs HBT工艺设计并实现了一种26GS/s单bit量化降速芯片。芯片采用树形级联架构,集成前端宽带比较器,综合优化各级降速单元拓扑,在功耗、速度各方面达到最优化。测试结果表明,芯片在26GS/s转换速率下,其SFDR大于8dBc,数据带宽达13GHz,显示出其在电子对抗及高速数据处理方面的潜力。 相似文献
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利用TSMC 0.18μm CMOS工艺设计了应用于SDH系统STM-64(10 Gb/s)速率级光接收机中的限幅放大器.该放大器采用了改进的Cherry-Hooper结构以获得高的增益带宽积,从而保证限幅放大器在10Gb/s以及更高的速率上工作.测试结果表明,此限幅放大器在10Gb/s速率上,输入动态范围为42dB(3.2mV~500mV),50Ω负载上的输出限幅在250mV,小信号输入时的最高工作速率为12Gb/s.限幅放大器采用1.8 V电源供电,功耗110mW.芯片的面积为0.7mm×0.9mm. 相似文献
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Radio-over-free-space (Ro-FSO) technology is a combination of free-space optics (FSO) and radio over fiber. It plays a significant role in radio-frequency signal transmission in mobile network communication through high-speed optical carrier without any licensing and costly cables. Photonic crystal fibers also play a significant role to deliver data at faster rate for short haul communication. This paper, for the first time to the author’s best knowledge, utilizes mode division multiplexing in conjunction with solid core PCFs to transmit \(2 \times 2.5\) Gbps–5 GHz data over 2.5 km free-space link. The results are reported in terms of bit error rate, spatial profiles of received modes, mode spectrum of modes and eye diagrams. Furthermore, proposed PCF-MDM-Ro-FSO transmission system is also reported under the impact of atmospheric turbulences. 相似文献
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Hai‐Han Lu Wen‐Shing Tsai Tzu‐Shen Chien Shih‐Hung Chen Yu‐Chieh Chi Che‐Wei Liao 《ETRI Journal》2007,29(2):162-168
A new scheme for bi‐directional HDTV/Gigabit Ethernet/CATV transmission over a hybrid dense‐wavelength‐division‐multiplexing passive optical network (DWDM‐PON) is proposed and demonstrated. It is based on injection‐locked vertical‐cavity surface‐emitting lasers and distributed‐feedback laser diodes as transmitters. Services with 129 HDTV channels, a 1.25 Gbps Gigabit Ethernet connection, and 77 CATV channels are successfully demonstrated over 40 km single‐mode fiber links. Good performance of bit error rate, carrier‐to‐noise ratio, composite second order, and composite triple beat is achieved in our proposed bidirectional DWDM‐PON. 相似文献
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本文提出了一种基于少模光纤布拉格光栅(Few-mode FBG)的模分复用通信系统,阐述了基于少模光纤布拉格光栅的模分复用/解复用原理,建立了2×2的模分复用实验系统,分别利用LP01和LP11模作为独立信道,实现了1.25 Gbps和622Mbps两路伪随机序列(PRBS)的10km传输实验,给出了传输后的眼图,分析了当激光器波长为1549.228nm时,实验系统的误码特性.实验验证了基于少模光纤布拉格光栅的模分复用通信系统的可行性,为进一步实现长距离高速率的模分复用通信奠定了实验基础. 相似文献
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A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2. 相似文献
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ZHANGCheng-an SONGQi-feng WANGZhi-gong 《半导体光子学与技术》2004,10(4):233-236
A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2. 相似文献