N掺杂MgZnO薄膜的p型导电稳定性研究

利用磁控溅射技术,以Mg0.06Zn0.94O为陶瓷靶材,制备了N掺杂p型Mg0.1 3Zn0.8 7O薄膜,薄膜的电阻率为42.45Ω·cm,载流子浓度为3.70×1017/cm3,迁移率为0.40cm2·V-1·s-1。研究了该薄膜p型导电性质在室温空气下随时间的变化情况。实验结果表明,薄膜的电阻率逐渐升高,载流子浓度降低,五个月以后,薄膜转变为n型导电,电阻率为85.58Ω·cm,载流子浓度为4.53×1016/cm3,迁移率为1.61cm2·V-1·s-1。真空热退火后重新转变为p型。结果显示,其p型导电类型的转变与在空气中吸附H2O或H2等形成浅施主有关。     

Current confinement and leakage currents in planarburied-ridge-structure laser diodes on n-substrate

An electrical device model for the planar buried-ridge-structure laser on n-type substrate is discussed. It takes into account the finite p-type contact resistivity, the two-dimensional current spreading, and the electron leakage current by drift and diffusion. Using this model, the influence of the relevant device parameters on the leakage current in InGaAsP/InP devices emitting at 1.3 μm is investigated. It is shown that leakage currents are negligible at room temperature if the contact stripe width does not exceed the sum of the active region width and the p-type confinement layer thickness, but they increase markedly with broader contact stripes and with contact resistivities above 10^-5 Ω-cm². The most important parameter influencing the leakage currents is the doping level of the P-InP confinement layer. With a p-type doping level of 1×10¹⁸ cm^-3, a p-type contact resistivity below 10^-5 Ω-cm² and a contact stripe width of 6 μm, the model calculations predict a maximum operation temperature exceeding 100°C. This agrees fairly well with experimental data proving that the rather simple planar buried-ridge-structure laser performs as well as more sophisticated devices incorporating current-blocking layers     

Fabrication of very high resistivity Si with low loss and crosstalk

We have used proton and As⁺ implantation to increase the resistivity of conventional Si (10 Ω-cm) and Si-on-quartz substrates, respectively. A high resistivity of 1.6 MΩ-cm is measured that is close to intrinsic Si and semi-insulating GaAs. Very low loss and cross coupling of 6.3 dB/cm and -79 dB/cm (10 μm gap) at 20 GHz are measured on these samples, respectively. The very high resistivity and improved rf performance are due to the extremely fast ~1 ps carrier lifetime stable even after a 400°C annealing for 1 h. Little negative effect on gate oxide integrity is also observed as evidenced by the comparable stress-induced leakage current and charge-to-breakdown for 30 Å oxides     

Isolation on Si wafers by MeV proton bombardment for RF integratedcircuits

This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 10¹⁷ cm^-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×10¹⁴ cm^-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×10¹⁵ cm ^-2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value     

Properties of nitrogen-implanted SOI substrates

Properties of nitrogen-implanted silicon-on-insulator (SOI) substrates prepared by implanting different doses of 200 keV nitrogen into 50-70 Ω-cm, p-type silicon substrates at a temperature of 500°C were studied. The distribution of nitrogen was studied using Auger electron spectroscopy. The electrical properties of the active overlayer were studied using Hall-effect measurements and capacitance-voltage depth profile analysis. The insulating integrity of the buried nitride was studied by directly measuring the leakage current from top to bottom through the substrate. Additionally, electric field strength and surface roughness measurements were performed. Nitrogen concentrations in the buried layer increased from below to above the stoichiometric value for Si₃N₄ for increasing dose in the range studied. Nitrogen-related n-type doping is observed in all samples examined, and the magnitude of the doping increased with the increasing implant dose. Insulating buried nitride layers are formed only in samples implanted with very high doses     

Large area GaInAsP solar cells grown by gas-source MBE on GaAssubstrates

Large area (1×1 cm²) Ga_0.84In_0.18 As_0.68P_0.32 solar cells with a band-gap of 1.50 eV were grown by gas-source MBE on GaAs substrates. Both n-on-p and p-on-n structures were fabricated and studied. The n-on-p cells showed significantly better total area conversion efficiencies (14.3% at AMO, 1-sun, with 20% of grid obscuration) than p-on-n structures (10.5%, same conditions) due to longer minority carrier lifetimes in the p-type base and heavily doped n-type emitter layers     

IPEL-a novel ion-implanted electrically programmable element

The programmable element consists of a metal/amorphous-silicon/crystalline-silicon structure in which the amorphous-silicon layer is created by high-dose ion implantation. Amorphization by the damage caused by the collisions of the energetic ions with the substrate increases resistivity of a normal contact to single-crystal silicon by many orders of magnitude. The specific resistance of a typical aluminum contact to heavily doped n-type silicon increases from 10^-6-10^-5 to 1-10 Ω-cm² at room temperature. Applying a sufficiently high voltage induces an irreversible transformation of the device into a low-resistance state. The postprogramming resistance can be as low as 100 Ω for a 3×3-μm² contact at room temperature     

CMOS on FZ-high resistivity substrate for monolithic integration ofSiGe-RF-circuitry and readout electronics

The choice of a highly resistive substrate for silicon millimeter-wave integrated circuits (SIMMWIC) imposed by the requirement of low RF-substrate losses requires the adaptation of a CMOS process on float zone silicon (FZ). A comparison of n- and p-channel devices realized on high resistivity substrate (p-type, 5000 Ω·cm) and standard CMOS substrates (CZ, n-type, 4-6 Ω·cm) is given. Using careful process design, we obtained device characteristics on FZ-substrates that are closely similar to those on standard material, thus allowing direct transfer of existing circuit designs     

Process and device characterization for a 30-GHz fT submicrometer double poly-Si bipolar technology using BF2-implanted base with rapid thermal process

Process and device parameters are characterized in detail for a 30-GHz f_T submicrometer double poly-Si bipolar technology using a BF₂-implanted base with a rapid thermal annealing (RTA) process. Temperature ramping during the emitter poly-Si film deposition process minimizes interfacial oxide film growth. An emitter RTA process at 1050°C for 30 s is required to achieve an acceptable emitter-base junction leakage current with an emitter resistance of 6.7×10^-7 Ω-cm², while achieving an emitter junction depth of 50 nm with a base width of 82 nm. The primary transistor parameters and the tradeoffs between cutoff frequency and collector-to-emitter breakdown voltage are characterized as functions of base implant dose, pedestal collector implant dose, link-base implant dose, and epitaxial-layer thickness. Transistor geometry dependences of device characteristics are also studied. Based on the characterization results for poly-Si resistors, boron-doped p-type poly-Si resistors show significantly better performance in temperature coefficient and linearity than arsenic-doped n-type poly-Si resistors     

High efficiency polycrystalline silicon solar cells by continuous plasma deposition and laser recrystallization

Solar cells of up to 12% efficiency have been fabricated on laser recrystallized fine grain polycrystalline silicon films produced by high pressure plasma (hpp) aided hydrogen reduction of trichlorosilane. The hpp system was operated in a continual mode to produce microcrystalline silicon films continually using finite size temporary molybdenum substrates. The major improvement over previous devices of this type is in the elimination of oxygen contamination during laser recrystallization. This resulted in a reduction in the dark excess junction current and improvement in minority carrier diffusion length. The devices are found to be diffusion limited, with diffusion current coefficients in the range of 3 × 10^-12to 5 × 10^-12A/cm²when the base resistivity was 0.4 to 0.5 Ω-cm p-type.     

Low emitter resistance GaAs based HBT's without InGaAs caps

Low emitter resistance is demonstrated for AlGaAs/GaAs heterojunction bipolar transistors using Pd/Ge contacts on a GaAs contact layer. The contact resistivity to 2-10×10¹⁸ cm ^-3 n-type GaAs is 4-1×10^-7 Ω-cm² . These are comparable to contact resistivities obtained with non-alloyed contacts on InGaAs layers. The non-spiking Pd/Ge contact demonstrates thermal stability and area independent resistivity suitable for scaled devices. The substitution of Pd/Ge for AuGe/Ni GaAs emitter and collector contacts reduced by an order of magnitude the emitter-base offset voltage at high current densities and increased f_t by more than 15% with significantly improved uniformity for devices with 2 and 2.6 μm wide emitters having lengths two, four and six times the width     

Electrical conduction and dielectric breakdown in aluminum oxideinsulators on silicon

Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160°C under dry O₂ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al ₂O₃ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al₂O₃ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q_0x, was less than 10¹¹ cm ^-2, and the interface trap density, D_it, was less than 10¹¹ cm^-2 eV^-1, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10^-7 A cm^-2, with a resistivity greater than 10 ¹² Ω-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications     

Monolithic photovoltaic PbS-on-Si infrared-sensor array

The growth of epitaxial narrow-gap PbS-on-Si substrates using a stacked CaF₂-BaF₂ intermediate buffer layer and the fabrication of linear arrays of photovoltaic infrared (IR) sensors in the PbS layer are discussed. The sensors of the array exhibit resistance-area products at zero bias of 3 Ω-cm² at 200 K (3.4-μm cutoff wavelength) and 2×10⁵ Ω-cm ² at 84 K (4-μm cutoff), with corresponding detectivities of 2×10¹⁰ and 1×10¹³ cm-√Hz/W, respectively     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

An approach for fabricating high-performance inductors onlow-resistivity substrates

Porous Si layers up to 250 μm in thickness are used to isolate spiral inductors from low resistivity substrates. Wafer curvature and secondary ion mass spectroscopy (SIMS) analysis are done to address the manufacturability issue of porous Si. Spiral inductors with a single level Al on 2 in, p-type substrates of 0.008 Ω-cm resistivity are demonstrated with Q<6 at 3 GHz for an L of ~8 nH. Large inductors with L~100 nH have been shown with the first resonance frequency at 1 GHz. The expected performance potential as well as factors that could be limiting the Q are discussed     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

隧道结AlGaInP发光二极管

报道了通过隧道结将衬底的导电类型从n型转变到p型,从而可以利用n型GaP作为以n型GaAs为衬底的AlGaInP发光二极管的电流扩展层.n型电流扩展层的电阻率低于p型电流扩展层的电阻率,这种结构改善了电流扩展层的作用,从而提高了发光二极管的光提取效率.对3μm GaP电流扩展层的发光二极管,实验结果表明,隧道结发光二极管的发光功率与具有相同基本结构的传统发光二极管相比,20mA时发光功率提高了50%,100mA时提高了66.7%.     

隧道结AlGaInP发光二极管

报道了通过隧道结将衬底的导电类型从n型转变到p型,从而可以利用n型GaP作为以n型GaAs为衬底的AlGaInP发光二极管的电流扩展层.n型电流扩展层的电阻率低于p型电流扩展层的电阻率,这种结构改善了电流扩展层的作用,从而提高了发光二极管的光提取效率.对3μm GaP电流扩展层的发光二极管,实验结果表明,隧道结发光二极管的发光功率与具有相同基本结构的传统发光二极管相比,20mA时发光功率提高了50%,100mA时提高了66.7%.     

Impact of CdTe/CdZnTe substrate resistivity on performancedegradation of long-wavelength n+-on-p HgCdTe infraredphotodiodes

For realizing HgCdTe focal plane arrays on alternate substrates (Si or GaAs), CdTe buffer layers are essential. Bulk CdTe/CdZnTe substrates are also used for LPE growth of HgCdTe. A model for the effect of the n-CdTe substrate resistivity on the quantum efficiency, η, and the dynamic resistance-area product, R_dA, of a n ⁺-on-p HgCdTe backside illuminated photodiode has been developed, taking into account the effect of the graded heterointerface between CdTe/CdZnTe and HgCdTe on the homojunction photodiode. The issue of how low the substrate/buffer layer resistivity can be, without degrading the performance of the photodiode, has been addressed. For low substrate resistivities, the R_dA can drop by about 50%, while the quantum efficiency decreases by about 5%. It has been found that as low as 2 Ω-cm for long wavelength IR photodiodes (cutoff wavelength 14 μm) is acceptable. To obtain the R_dA and η from the band profile, a linear approximation has been used in which the interface barrier region has a constant electric field, while the bulk of the epilayer has no electric field. General expressions have been derived for the R_dA and η in this two-region model. Our solutions are valid for both high and low electric fields, unlike previously derived solutions in the literature valid either in the one-region low-field case or the two-region, high-field approximation