95GHz低相噪锁相源技术研究

基于毫米波锁相源相位噪声理论,明确指出采用低相位噪声的微波频率源可以有效改善毫米波锁相源相噪指标。利用低相位噪声的微波倍频源,结合谐波混频方式,设计出95GHz低相位噪声锁相频率源。测试结果表明,其相位噪声可以低至-90.44dBc/Hz@10kHz,验证了该设计方案的可行性。     

一种毫米波宽锁定范围的注入锁定倍频器设计

为提高毫米波段倍频器在低功耗下的工作带宽,采用IHP130 nm SiGe BiCMOS 工艺,设计了一种采用双端注入技术的毫米波宽锁定范围注入(DEI)锁定倍频器。该注入锁定倍频器主要由谐波发生器和带有尾电流源的振荡器构成,由巴伦产生差分信号双端注入振荡器的形式提高三次谐波注入强度,使其在E、W 等波段输出宽锁定范围和良好相位噪声性能的三倍频信号。仿真结果表明,注入锁定倍频器在工作电压为1.2 V,输入信号功率为0 dBm时,其锁定范围在57~105 GHz 内。在相同工作电压和输入信号功率下,输入频率为32 GHz 时,一次、二次和四次谐波抑制大于20 dBc,功耗为9.1 mW。     

Ka波段Gunn锁相源的研究

本文对Ka波段锁相源作了分析和研究,探讨了毫米波锁相环路的稳定性和相位超前补偿问题。采用双锁相环路研制了腔稳偏压调压控振荡器(VCO)、高次倍频器、低相噪微波锁相源等关键部件,采用了表面安装技术(SMT)和高密度组装技术,使研制的毫米波锁相源具有小型化、低相位噪声、高稳定度等特点。     

Phase Locking of 2-mm Wave Sources Upon High-Order IMPATT Multipliers

We describe experiments resulting in the phase locking of two electrically tunable 2-mm wave sources based on active high-order IMPATT multipliers. Phase locking modes were tested on a pair of identical multiplying sources (master and slave) with the tuning ranges 138.5+/?1.5 GHz (master) and 140.0+/? GHz (slave). The phase lock loop (PLL) system is used to lock the slave source to the master source. The multipliers of this type can translate the spectra of highly stable centimeter-wave oscillators to any part of the millimeter range with the output power 100÷20 mW over the 30 to 140 GHz range without additional amplification. The phase locked sources operate over a 3% frequency band with low phase noise and rapid frequency tuning. The amplitude-frequency characteristics of the sources are presented with the locking-mode signal spectra.     

Phase Noise Analysis and Estimate of Millimeter Wave PLL Frequency Synthesizer

Phase noise is an important index in evaluating the performance of millimeter wave (MMW) frequency source. Because of the high frequency, it is difficult to measure its phase noise directly. So it is very necessary to find new methods for estimating it effectively and easily. In this paper, the main factors affecting phase noise of MMW PLL frequency source are analyzed, and then a new method to estimate the phase noise is presented, which is based on the comparison of the phase noise of microwave phase-locked frequency source with phase-locked intermediate frequency in MMW phase-locked loop. In order to demonstrate the validity of this method of phase noise estimate, it is applied to estimate the phase noise of 95GHz double PLL frequency synthesizer. The result shows that the theoretical estimate value is well coincident with the experimental value.     

一种基于偏移源的频率合成技术分析

针对一种基于偏移源的频率合成技术,建立了锁相环(PLL)线性模型,对相位噪声和杂散信号性能进行分析。从分析结果看,在锁相环反馈支路中使用一个偏移源将压控振荡器(VCO)输出信号下混频至一个较低的中频,从而将锁相环的环路分频比大大降低,使改善后的锁相环噪底达到-135 dBc/Hz。介绍了偏移源和主环的关键合成技术,结合工程应用设计的基于偏移源的C频段频率合成器,相位噪声偏离载波10 kHz处≤-99 dBc/Hz,偏离载波100 kHz处≤-116 dBc/Hz,杂散小于-70 dBc。     

某型多调制方式低相噪毫米波频率源设计

介绍了一种低相噪、多调制方式毫米波频率源方案,采用直接数字频率合成(DDS)+锁相环(PLL)技术,通过引入FPGA解决了同时产生多调制编码单元的难题。详细分析了数字调制编码单元,给出了软件控制流程、m序列Modelsim仿真结果以及环路滤波器设计参数。实测结果表明,调制信号中心频率30 GHz,输出功率大于4 dBm,相位噪声优于-100 dBc/Hz@100 kHz。     

W波段低成本数字通信系统

在毫米波频段,由于振荡器的频率漂移很大,常常采用锁相源,使系统成本大大增加.本文采用频率跟踪方案,实现了W波段数字通信系统,并详细描述了系统的关键技术.对8448kbit/s的数字通信实验表明,该系统的门限电平比采用锁相源的系统仅差3dB.该系统方案简单,成本大大降低.实验还表明,该方案中锁相环的采用没有对解调波形产生明显影响.     

E波段倍频放大模块设计

E波段是毫米波中非常重要的频段,也是较为缺乏研究的频段。E波段可三倍频至亚毫米波频段,其中220 GHz是大气吸收窗口,具有非常重要的研究价值。基于此,文中设计了一款E波段倍频放大模块,为220 GHz太赫兹发射机提供三倍频源信号,该模块输入频率为11.1~13.34 GHz,输出频率为66.6~80 GHz,输入功率为4~5 dBm,输出功率>18 dBm,增益>13 dB,具有较好的输出功率平坦度。该模块的成功研制为亚毫米波收发模块提供了功率源条件。     

声表面波射频识别系统的FMCW信号源设计

频率调制连续波(FMCW)的产生(即FMCW信号源)是声表面波射频识别系统频域采样阅读器的重要组成部分。为了满足扫频速度、带宽和线性度等要求,采用直接数字频率合成器(DDS)与锁相环(PLL)混频,并结合IQ调制的方式设计了超高频FMCW信号源。实际制作了信号源电路,DDS芯片输出I、Q两路正交信号,并分别以差分形式传输至IQ调制芯片进行上变频。测试了DDS输出信号的差分、正交特性,分别对信号源产生的单频信号和扫频信号进行了测试。最后搭建系统对声表面波标签进行测试。测试结果表明信号源设计的有效性。     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

Phase Lock-In of MM/SUBMM Backward Wave Oscillators: Development, Evolution, and Applications

The development and evolution of a Phase-Lock Loop (PLL) system up to the highest frequencies of Backward Wave Oscillators (BWO) is considered starting from the first submillimeter BWO PLL in 1970. Improvements and increase of working range near to Terahertz are followed. Development of the series of commercial BWO-based millimeter wave frequency synthesizers, extension of the BWO PLL beyond Terahertz as well as recent progress in fast millimeter wave frequency synthesizers are described. Applications of BWO PLL systems for physical and technical measurements are discussed and some proposals for the next generation of BWO-based synthesizers are presented.     

Ka波段直接数字调频锁相源

本文结合调制和锁相理论,论证了数字信号直接调制锁相源的可行性。研制的Ｋａ波段锁相耿氏振荡器能实现２＾１５级８４４８ｋｂｉｔ／ｓ的数字信号直接调频。该技术能大大降低通信系统的成本。     

Narrow-band modulation of semiconductor lasers at millimeter wavefrequencies (>100 GHz) by mode locking

The possibility of mode locking a semiconductor laser at millimeter wave frequencies approaching and beyond 100 GHz was investigated theoretically and experimentally. It is found that there are no fundamental theoretical limitations in mode locking at frequencies below 100 GHz. At these high frequencies, only a few modes are locked and the output usually takes the form of a deep sinusoidal modulation which is synchronized in phase with the externally applied modulation at the intermodal heat frequency. This can be regarded for practical purposes as a highly efficient means of directly modulating an optical carrier over a narrow band at millimeter wave frequencies. Both active and passive mode locking are theoretically possible     

基于HMC833低相噪低杂散频率源的设计

航天靶场中射频(RF)转发系统对频率源相位噪声的要求很高,因此有必要研究低相噪、低杂散、低功耗、小步进的频率源。为了适应现代航天靶场的要求,选用HMC833LP6GE锁相环芯片进行频率源设计,并用C8051F314单片机对锁相环芯片进行控制,设计出了一款性能优越的频率源。测试结果表明在合理的参数配置条件下,频率源可以满足系统的各项要求。     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

A Novel Quasi-Optical Frequency Multiplier Design for Millimeter and Submillimeter Wavelengths

This paper describes a novel design for millimeter and sub-millimeter wavelength varactor frequency triplers and quadruplers. The varactor diode is coupled to the pump source via waveguide and stripline impedance matching and filtering structures. Output power at the various harmonics of the pump frequency is fed to quasi-optical filtering and tuning elements. The low-loss quasi-optical structures enable near-optimum control of the impedances seen by the varactor diode at the idler and output frequencies, resulting in efficient high-order harmonic conversion. A minimum efficiency of 4 percent with 30-mW input power has been obtained for a tripler operating between 200 and 280 GHz, with a peak efficiency of 8 percent between 250 and 280 GHz. Another tripler, designed for the 260-350-GHz band, gave a minimum conversion efficiency of 3 percent with 30-mW input power, with a peak efficiency of 5 percent at 340 GHz.     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

基于DDS 与PLL 的C 波段宽带线性扫频源

利用直接数字频率合成(DDS)和锁相环(PLL)技术相结合的混合频率合成方案,研制了一种C波段宽带、高频率分辨率、快速线性扫频的频率源。为了给PLL 提供低相位噪声的宽带扫频参考信号,选用ADI 的DDS芯片AD9914,并利用阶跃恢复二极管(SRD)高次倍频电路结合二倍频器产生高达3400 MHz 的时钟信号。通过上位机配置AD9914 内部频率调谐字和数字斜坡发生器,产生512.5-987.5MHz 的扫频参考信号,其频率分辨率可精细到赫兹量级。选用低附加噪声的鉴相器和宽带VCO 芯片设计C 波段锁相源,在宽带工作频率范围内对DDS 扫频信号进行快速跟踪,并有效抑制杂散信号。实测结果表明,该扫频源工作频率为4. 1- 7. 9 GHz,在频率分辨率配置为0. 38 MHz 时,单向扫频周期为1 ms,扫频线性度为1. 58×10-6 。单频点输出时相位噪声优于-114 dBc/ Hz@ 10 kHz和-119 dBc/ Hz@ 100 kHz,杂散抑制优于69 dBc。     

8mm小型化低相位噪声锁相源

依据小型化、低相位噪声原则设计了毫米波锁相源．在实现方案中，选用了高性能的锁相环、分频器和集成ＶＣＯ等器件；结构上采用了毫米波高密度组装技术和ＳＭＴ技术，使研制成功的毫米波锁相源具有体积小、相位噪声低、入锁快和可靠性好等特点，可适用于机载、弹载等许多场合．