富铟熔体生长InP单晶的晶体缺陷及物理特性

通过磷注入法合成并利用液封直拉法(LEC)生长了富铟InP单晶,将晶锭进行定向切割、研磨和抛光,得到InP抛光片.用金相显微镜、扫描电镜、快速扫描光荧光谱(PL-Mapping)技术、高分辨率XRD射线衍射技术研究了富铟非掺InP单晶样品特性.结果表明,在富铟条件下生长的InP单晶会出现富铟夹杂,这种富铟夹杂可导致其周围位错密度升高,同时富铟夹杂在晶片内分布也是不均匀的,在晶片中心部分富铟夹杂的密度高,在边缘部分密度低.对富铟夹杂形成及不均匀分布的原因进行了分析,讨论了富铟夹杂对PL-Mapping发光峰峰值的影响.     

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

微光器件铟封漏气因素分析

为解决微光管光电阴极与管体铟封漏气问题,采用扫描电镜和X射线能谱仪对铟材和封接过程工艺质量进行全面分析,结果表明造成铟封漏气的根本原因是铟量小,铟表面氧化和吸附的杂质污染造成的,与铟纯度无关。采取提高真空度,改进化铟工艺,控制铟高温外流等措施解决了阴极与管体铟封漏气问题,使气密性成品率大于90%。     

高功率半导体激光器互连界面可靠性研究

随着高功率半导体激光器（HPLD）在极端环境中的应用越来越广泛，互连界面的可靠性已成为制约其性能和寿命的关键瓶颈之一。文中利用有限元方法（FEM）对传导冷却（CS）高功率半导体激光器巴条互连界面在-55~125℃热冲击条件下的失效行为和寿命进行了模拟与分析。基于粘塑性Anand本构模型和Darveaux能量积累理论，对比了热冲击后界面层边缘及中心位置铟互连界面的可靠性，发现互连界面边缘的应力最大，达到0.042 5 GPa；相应的边缘位置的寿命最短，只有3 006个周期，即边缘位置为互连界面的最危险单元。预测了采用铟、金锡合金和纳米银焊膏封装的半导体激光器巴条的寿命，计算出铟、金锡合金和纳米银焊膏三种不同键合材料在边缘位置的寿命分别为3 006、4 808和4 911次循环，表明纳米银焊膏和金锡合金在热冲击条件下具有更长的寿命，更适合于用于极端环境的高功率半导体激光器封装。     

InSb红外焦平面探测器十字盲元问题的研究

InSb红外焦平面探测器在中波红外波段占据重要地位,但十字盲元问题严重降低了探测器的性能。通过聚焦离子束定位剥离手段,发现了十字盲元区域的铟凸点失效。进一步检测发现,铟凸点制备参数欠佳。通过改进铟凸点形状和增加高度,加强了焊接面的牢固度。此后发现极少InSb器件存在十字盲元问题。在80℃下对铟凸点改进后的InSb红外器件进行了14天烘烤。经测试,十字盲元数目保持不变,铟凸点的可靠性较好。改进铟凸点制备技术可有效解决十字盲元问题。互连失效是十字盲元问题的主要原因。以此类推,该方法可解决所有InSb红外器件的十字盲元问题。     

叠层片式电感的短路失效模型

通过对叠层片式电感器短路失效样品的电性能测试和显微分析可知,叠层片式电感器的短路主要为引出端短路和介质层短路,其根源在于铁氧体的粒度、浆料分散性、丝网制作及烧结工艺,通过完善球磨工艺、改变加料方式、减少丝网乳胶厚度、控制成型和烧结工艺,可使短路率由15%以上降低为6%以下。     

平行板电容器中介质受力问题的讨论

用虚功原理计算介质块在平行板电容器中的受力，是一道经典电磁场例题。在忽略边缘效应的情况下，垂直方向的电场如何产生了一个横向的作用力？本文回顾和分析了历史上的一些讨论，明确了边缘场对介质中电偶极矩的作用是介质受到横向力的根本原因，解释了为什么使用虚功原理可以忽略边缘效应，讨论了介质分界面的受力问题，澄清了一些错误的认识。     

多层介质电容失效分析

针对GaAs MMIC因电容失效而导致性能异常的问题,分析了电容失效模式及失效机理。对GaAs MMIC中多层介质电容的制作过程进行了重点监控,分析了电子束蒸发工艺缺陷对多层介质电容失效的影响。基于扫描电子显微镜(SEM)及能谱仪(EDX)分析,研究了电容基板金属颗粒对电容失效的影响。结果表明,电子束蒸发工艺产生的金属颗粒造成短路是电容主要失效模式。蒸发难熔金属时,在金属源形成的深坑导致蒸发速率瞬时增大,产生的大量金属颗粒造成电容极板短路,从而导致电路性能异常。最后,对金属蒸发工艺参数进行优化,采用分段蒸发增加熔源过程的方法降低了电容失效率。     

双光栅结构薄膜太阳能电池的优化

为了提高单晶硅薄膜太阳能电池短路电流密度和转换效率, 采用在单晶硅薄膜太阳能电池正背面分别集成硅介质光栅和铝金属光栅的方法, 并利用有限时域差分法软件仿真研究了两种光栅的周期、厚度、占空比对单晶硅薄膜太阳能电池短路电流密度和光转换效率的影响。结果表明, 通过优化可得当正背面光栅都处于最优值时(介质光栅占空比F=0.8、介质光栅周期P=0.632μm、介质光栅厚度h_g=0.42μm; 金属光栅占空比F₁=0.9、金属光栅周期P=0.632μm、金属光栅厚度h_m=0.005μm), 短路电流密度可达35.15mA/cm2, 转换效率为43.35%;将最优光栅单晶硅薄膜太阳能电池与传统单晶硅薄膜太阳能电池对比, 无论是光程路径还是吸收效率, 光栅单晶硅薄膜太阳能电池都有显著的提高。这为以后制备高性能薄膜太阳能电池提供了理论指导。     

多层瓷介电容器失效模式和机理

系统介绍了开路、短路和电参数漂移这三种主要的MLCC失效模式,以及介质层内空洞和电极结瘤、介质层分层、热应力和机械应力引起介质层裂纹、其他微观机理等五种主要的失效机理。针对MLCC的失效分析技术,从生产工艺和使用设计上提出了预防MLCC失效的措施。     

基于CoolSET—F3的反激电源的分析和设计

文章从电路结构、芯片功能等方面对新型电源控制芯片CoolSET与常用芯片UC3842和NCP1207进行了比较,CoolSET—F3系列芯片将PWM发生器、短路保护、前沿消隐等多种功能集成于芯片内部,电路结构更简单,功能更完备。文中采用CoolSET芯片设计并试验了市电输入、六路输出的反激电源。试验结果表明,采用CoolSET芯片提高了变换器的效率,适应于微型开关电源的研究。     

Electromigration and electrochemical reaction mixed failure mechanism in gold interconnection system

Power bipolar devices with gold metallization experience high failure rates. The failures are characterized as shorts, detected during LSI testing at burn-in. Many of these shorted locations in the chip are the same for the failed devices. From a statistical analysis for wafer lots, it is found that the short failure rate is higher for the lots with thinner SiON interlayer dielectric films. Cracks are commonly observed in the SiON films at step edge portions of the device. The SiON film is locally turned to Au–Si eutectic at short positions by the reaction of Au with the SiON film and the reaction is only generated at specific step edge portions, i.e., at step edge on emitter electrodes in driver transistors and/or at cross-points of power lines. Based upon these results, a new electromigration and electrochemical reaction mixed failure mechanism is proposed for the failure.     

ICP dry etching ITO to improve the performance of GaN-based LEDs

In order to improve the light efficiency of the conventional GaN-based light-emitting diodes(LEDs), the indium tin oxide(ITO) film is introduced as the current spreading layer and the light anti-reflecting layer on the p-GaN surface.There is a big problem with the ITO thin film’s corrosion during the electrode preparation.In this paper,at least,the edge of the ITO film was lateral corroded 3.5μm width,i.e.6.43%—1/3 of ITO film’s area. An optimized simple process,i.e.inductively couple plasma(ICP),was introduced to solve this problem.The ICP process not only prevented the ITO film from lateral corrosion,but also improved the LED’s light intensity and device performance.The edge of the ITO film by ICP dry etching is steep,and the areas of ITO film are whole. Compared with the chip by wet etching,the areas of light emission increase by 6.43%at least and the chip’s lop values increase by 45.9%at most.     

具有安全保护的高性能电荷泵

设计了一种能有效控制电流过冲与输出短路电流的高性能电荷泵稳压器,它通过改变误差放大器输出来控制电荷泵开关管电流,使得电荷泵在启动阶段具有输出短路控制,在正常工作时能够有效抑制电流过冲.理论分析和仿真结果表明,采用此结构的电荷泵稳压器输出短路电流最大值为110 mA,远小于电荷泵正常工作时开关充电电流500mA.     

用于双极电路ESD保护的SCR结构设计失效分析

针对目前双极电路的ESD保护需求,引入SCR结构对芯片进行双极电路ESD保护。通过一次流片测试,发现加入SCR结构的电路芯片失效,SCR结构的I-V特性曲线未达到要求。从设计问题和工艺偏差两方面入手,分析了失效原因,通过模拟仿真,验证了失效是因为在版图设计时为节省版图面积,将结构P阱中NEMIT扩散区域边上用来箝位的电极开孔去掉造成的,并非工艺偏差导致的。通过二次流片测试,验证了失效原因分析的正确性,SCR器件结构抗ESD电压大于6kV,很好地满足了设计要求。     

表面等离子体共振增强ZnO/Ag薄膜发光特性研究

为了提高氧化锌光致发光强度,以磁控溅射氧化锌/银复合薄膜为研究对象,系统地研究了氧化锌薄膜的光学性质。实验中首先在硅衬底上用射频磁控溅射的方法沉积氧化锌/银复合薄膜,作为对比,同时沉积了一层氧化锌薄膜。通过扫描电子显微镜和原子力显微镜对样品的形貌及成份进行表征,并且在室温下测试样品在300~800 nm波长范围内的光致发光光谱。实验结果表明:所制得样品为均匀分布的氧化锌纳米薄膜,纯氧化锌光致发光光谱结果显示有波长位于378 nm左右的紫光、470 nm左右的蓝色发光峰存在,加入银薄膜后,氧化锌可见光区和紫外光区的光致发光光谱强度均有所增强,而且紫外光峰位出现了红移。实验结果结合样品吸收谱对光致发光机理的分析作了进一步的分析。     

Retina‐Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch‐Selective Resistive Network

A bio‐inspired vision chip for edge detection was fabricated using 0.35 μm double‐poly four‐metal complementary metal‐oxide‐semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of 160×120 pixels has been fabricated in 5×5 mm² silicon die. It shows less than 10 mW of power consumption.     

Analysis of Failure Mechanism in Anisotropic Conductive and Non-Conductive Film Interconnections

Failure behaviors of anisotropic conductive film (ACF) and non-conductive film (NCF) interconnects were investigated by measuring the connection resistance. The four-point probe method was used to measure the connection resistance of the adhesive joints constructed with Au bump on Si chip and Cu pad on flexible printed circuit. The interconnection reliability was evaluated by multiple reflow process. The connection resistance of the ACF joints was markedly higher than that of NCF joints, mainly due to the constriction of the current flow and the intrinsic resistance of the conductive particles in ACF joints. The connection resistances of both interconnections decreased with increasing bonding force, and subsequently converged to about 10 and 1 mOmega at a bonding force of 70 and 80 N, for the ACF and NCF joints, respectively. During the reflow process, two different conduction behaviors were observed: increased connection resistance and the termination of Ohmic behavior. The former was due to the decreased contact area caused by z-directional swelling of the adhesives, whereas the latter was caused by either contact opening in the adhesive joints or interface cracking.     

SMT在微波集成电路中的应用

本文论述了微波集成陶瓷基片焊接ＳＭＤ，ＳＭＣ出现的问题，并给予分析。提出了解决的措施。     

A 2-ns detecting time, 2-μm CMOS built-in current sensingcircuit

Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns