Design of AB2 in Galois Fields Based on Multiple-Valued Logic

A new AB~2 operation in Galois Field GF(2~4)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2~k).     

Systolic B –1 Circuit in Galois Fields Based on a Quaternary Logic Technique

In order to improve the circuit complexity and reduce the long latency of B~(-1) operations,a novel B~(-1) operation in Galois Field GF(24) is presented and the corresponding systolic realization based on multiple-valued logic(MVL) is proposed. The systolic structure employs multiplevalued current mode(MVCM) by using dynamic source-coupled logic(SCL) to reduce the initial delay and the transistor and wire counts. The performance is evaluated by HSPICE simulation in 0.18 μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature. The initial delay and the sum of transistors and wires in our MVL design are about 43% and 13% lower, respectively, in comparison with other corresponding binary CMOS implementations. The systolic architecture proposed is simple, regular, and modular,well suited for very large scale integration(VLSI) implementations. The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2~k).     

Design of quaternary logic circuits based on source-coupled logic

In order to improve the performance of arithmetic very large-scale integration ( VLSI) system,a novel structure of quaternary logic gates is proposed based on multiple-valued current mode ( MVCM) by using dynamic source-coupled logic ( SCL) . Its key components,the comparator and the output generator are both based on differential-pair circuit ( DPC) ,and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0. 18 μm CMOS technology. The power dissipation,transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.     

采用混合MTJ/CMOS和SABL结构的密码算法电路设计

为了在提高轻量级密码算法(Lightweight cipher algorithm, LWCA)电路安全性的同时降低功耗,提出了一种磁隧道结(Magnetic tunnel junction, MTJ)/CMOS混合结构查找表(Look up table, LUT)电路,该结构通过与感测放大器逻辑(Sense amplifier based logic, SABL)元件配合可以实现完整的PRESENT-80加密算法电路。设计将MTJ器件引入防护电路设计中,进而提出了一种基于混合MTJ/CMOS结构的双轨查找表(Look-up table, LUT)电路结构。首先,基于40 nm CMOS工艺库和MTJ器件仿真模型,使用新提出的双轨查找表结构设计了加密算法电路工作过程中所需要的关键S-box电路并通过了仿真验证。然后,利用该电路和敏感放大器逻辑元件电路结构组合设计了PRESENT-80密码算法的完整电路。最后对所设计的电路模型进行了相关性功耗分析攻击(CPA)攻击,同时为了方便进行对比研究,还对使用传统CMOS单轨和SABL双轨结构实现的PRESENT-80加密算法电路模型进行了相同条件...     

PSpice9.2在TTL和CMOS反相器中的应用

应用PSpice9.2仿真软件对TTL和CMOS反相器的逻辑特性和电气特性进行了分析,结果表明,PSpice9.2可用于TTL和CMOS反相器的分析和设计,并可加深对TTL和CMOS逻辑门电路工作原理的理解.     

基于NPN-NPN的二值BiCMOS电路设计

首先应用传输电压开关理论,提出了一种基本的基于NPN-NPN的BiCMOS驱动电路结构。然后,基于该驱电路动结构设计了二值BiCMOS非门电路,与非门电路和或非门电路结构。通过HPSPICE软件模拟,结果表明所设计的电路具有正确的逻辑功能。     

Design of a trimmed current reference with a low temperature drift

Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference circuits. Based on device mismatch models, a current reference I_ref with adjustable output current from 15μA to 80μA is designed. A compensated circuit is used to reduce the temperature drift. To achieve more accurate current reference, an 8bit bi-directional trimming array with 127 current levels is proposed. This digitally programmable array is binary weighted for accuracy and flexibility. Simulation shows that the temperature coefficient is 26ppm/℃ over the wide range of -40℃ to 120℃when the output current is 15μA. Based on the CMOS 0.13μm technology, the measurement results show that the trimmed range and precision for current reference are -14.3％·I_ref～14.3％·I_ref and 0.11％·I_ref, respectively. The circuit could be applied to high precision A/D and D/A converters.     

Design of the writing circuit with a low supply voltage for the spin-transfer torque random access memory

A writing circuit with a low supply voltage for the spin transfer torque magnetic random access memory (STT-MRAM) is proposed to reduce the writing power consumption. Using the combination of the column selecting and the isolation between writing and reading operation, the writing circuit with a low supply voltage decreases the resistor value of the writing branch and the value of the reading current. Therefore the switching power efficiency and the reliability can be improved. By using an accurate compact model of the 65nm magnetic tunnel junction (MTJ) and a commercial CMOS design-kit, mixed transient and statistical simulations have been performed to validate this design. Simulation results indicate that the proposed circuits can decrease the writing power consumption and improve the reliability.     

基于SET/MOS混合结构的4-2编码器设计

基于单电子晶体管（SET）的库仑振荡效应、多栅输入特性和相移特性,实现了SET/MOS混合结构的或门逻辑,并利用该或门逻辑实现了4-2编码器。利用HSPICE对所设计电路进行仿真验证,仿真结果表明该电路能够实现4-2编码器的编码功能。与纯CMOS编码器相比,该SET/MOS混合电路仅由2个PMOS管、2个NMOS管和2个SET构成,具有结构简单、尺寸小、集成度高的优点。     

应用于多值逻辑的双传输管逻辑网络综合

为实现静态电压型多值逻辑电路, 提出了一种采用双传管逻辑(DPL)结构的设计方案及综合方法. 在该设计方案中,文字运算电路也是采用普通MOS管来实现, 而无需对阈值作任何的调整. 通过建立描述双传输管开关状态与信号之间相互作用关系的传输运算表示式,实现了对电路的有效综合. 对三值单变量函数电路、三值与/与非门、或/或非门、三值模3乘法器和三值T门的设计结果,验证了所提出方法的有效性. 在此基础上总结出了采用DPL设计三值电路的反演法则和对偶法则，使用这些法则可在不改变电路结构的基础上方便地得到相应的补函数和对偶函数电路, 从而增强电路的功能. 所提出的设计方法和法则可用于对三值复杂函数的综合.     

EWB在数字电路教学中的应用

介绍了仿真软件EWB(Electronics Workbench)的数字逻辑电路仿真功能与实现方法。四个典型数字电路仿真分析表明了EWB为数字电路分析设计提供了实用、高效的仿真环境,EWB的应用改善了数字电子技术教学手段。     

新颖的余数系统到二进制系统转换方法

传统的余数系统(RNS)到二进制系统(R/B)转换电路中的大位宽操作削弱了RNS的并行特性。针对这一问题,提出了基于数值缩放(Scaling)的R/B转换算法和余数系统2k缩放并行实现的方法。同常见余数基R/B转换算法的比较分析结果表明,所提出的算法使R/B转换中的最大运算位宽限制在最大余数基位宽内,从而消除了R/B转换中可能带来的系统并行度损失;此外,该转换算法可实现有符号RNS到二进制补码系统(TCS)的转换,且不限于具体余数基形式,具有一定的通用性。     

Synthesis and crystal structure of bis(1,3-diisopropyl-4,5-dimethylimidazolium) hexatungstate

The title compound bis(1,3-diisopropyl-4,5-dimethylimidazolium) hexatungstate,[C_11H_21N_2]_2[W_6O_19],was synthesized and characterized by single-crystal X-ray diffraction,IR and elemental analysis.It crystallizes in the monoclinic system,space group P2_1/n with a=1.112 84(14),b=1.283 84(17),c=1.293 28(17)nm,β=96.410(2)°,V=1.836 2(4)nm~3,C22H42N4O19W6,Mr=1 769.70,Dc=3.201 g/cm3,F(000)=1 596,Z=2,μ(Mo Kα)=18.797 mm-1,the final R=0.031 3,wR=0.059 8for observed reflections(I2σ(I)).     

结合半加图的算术电路等价性验证技术

为了克服现有等价性验证技术难以快速验证复杂算术电路的局限性,提出了一种利用综合引擎分析并再现算术电路优化过程的算法．该算法结合了乘法器的编码方式识别技术、加法电路的半加树提取技术和部分积加法电路的架构识别技术来提取乘法电路的实现结构,以此生成与实现电路结构相似且逻辑正确的网表．针对算术电路结构的相似性,仅分析低位输出的电路架构以降低算法复杂度．实验结果表明,与传统的算术电路验证算法相比,该算法可以明显提高算术电路的验证速度,并且可以直接结合到现有的寄存器传输级（RTL）和门级网表的验证流程中,从而提高了算术电路的验证能力．     

G比特级通用可逆计数器的CMOS电路设计

在数字锁相环中,可逆计数器是组成数字滤波器的关键电路,本文讨论了通用可逆计数器的工作原理,推导出了电路的逻辑表达式,并设计了五位且可扩展的可逆计数器的电路原理图。采用仿真器NC-Verilog进行了功能验证,同时采用CMOS电路实现了整体功能,最后利用Cadence的Spectre给出了该电路在0.18um CMOS工艺下的晶体管级仿真结果,电路最高工作频率可以达到1.25GHz;而利用Synopsys的Design Compiler对规范书写的Verilog模块在相同工艺下进行逻辑综合得到的电路最高频率只能达到800MHz。     

CMOS电路泄漏功耗估算与降低方法研究

为了减小深亚微米互补金属氧化物半导体（CMOS）电路待机模式下的泄漏功耗，须寻找使电路泄
漏功耗最低的最小泄漏向量（MLV）.为此，提出了一种基于泄漏功耗库的线性规划功耗模型，并在此基
础上提出了基于改进的遗传算法搜索电路MLV的方法.线性规划模型根据电路泄漏功耗库中各个基本单元
的状态对应的泄漏功耗值，来估算整个门级电路的泄漏功耗.遗传算法利用线性规划模型作为评价函数，
通过对输入向量集进行自然选择、交叉、变异操作，搜索使电路泄漏功耗最低的MLV.仿真结果表明，搜
索到的MLV可以显著降低电路的泄漏功耗，而且易于实现，能够应用于超大规模集成电路泄漏功耗的估计
和降低.     

CMOS锁相环中快速鉴相鉴频器的设计

摘要：为了实现高速锁相环电路,通过分析经典CMOS锁相环的鉴相鉴频器,针对其延迟时间过长的问题,设计了可用于CMOS锁相环中的快速鉴相鉴频器．整个电路采用了0．13μmCMOS工艺,通过HSpice仿真软件测试表明,该快速鉴相鉴频器与经典鉴相鉴频器相比,延迟时间可以缩短一半．     

基于部分簇能量互补逻辑的MRF电路设计

功耗是电路设计的关键性问题之一,低功耗下的稳定性问题逐渐成为电路设计的热点和挑战,基于马尔科夫随机场（MRF）的低功耗设计从能量的角度出发有效地解决了电路的容错问题,但是其单逻辑的单元结构面积和复杂度制约了该技术在大规模集成电路的应用。该文提出了一种基于部分簇能量的MRF电路设计方法（PMRF）,并结合互补逻辑的特点来实现多逻辑结构,面积共享的同时一方面补偿由于部分簇能量带来的性能损失,一方面化简马氏随机场电路设计在较大规模电路设计中的面积和复杂度瓶颈问题。对比传统MRF电路设计,该文用PMRF方法设计了超前进位加法器结构,在低功耗仿真中具有20%的性能提升,并在65 nm TSMC版图实现后取得29%的面积节约和86%的功耗节约。     

四值绝热动态D触发器开关级设计

研究绝热电路和多值触发器,提出一种四值绝热动态D触发器设计方案.该方案采用多阈值金属氧化物半导体MOS管控制技术和开关信号理论,推导四值绝热动态D触发器文字运算电路结构式,由文字运算电路控制四值绝热逻辑信号产生,实现动态D触发器的四值输出,并在此基础上设计具有记忆功能的触发型四值绝热正循环门.通过PSpice模拟软件验证该设计电路逻辑功能正确,在55.6 MHz工作频率下,与常规CMOS四值动态D触发器相比,节省功耗约90%.     

用于低功耗A/D转换器的运算跨导放大器设计

设计了一种适用于采用级间共用运放技术的10bit流水线A/D转换器(ADC)的低功耗全差分运算跨导放大器(OTA).该放大器由一个改进的折叠共源共栅结构和一个套筒共源共栅结构共同组成,利用时钟控制,使ADC的采样保持和余量增益电路正常工作并满足其性能要求.基于0.6μmCMOS工艺对电路进行了设计,并利用HSpice软件对电路进行了仿真.仿真结果表明,该放大器在采样保持和奇数级电路中开环增益为60dB,偶数级电路开环增益为50dB,总功耗仅为4.5mW,满足低功耗ADC所要求的性能指标.