A 20-MHz bandwidth, 75-dB dynamic range,continuous-time delta-sigma modulator with reduced nonidealities

This letter presents a 4-bit continuous-time delta-sigma modulator (CT-DSM) fabricated using a 65-nm CMOS process. The circuit is designed for wide-bandwidth applications, such as those related to wireless communications. This CT-DSM has an oversampling ratio of 16 with a 640-MHz sampling frequency. To reduce the clock jitter sensitivity and excess loop delay effect, the first DAC pulse is a nonreturn-to-zero (NRZ)–type pulse, whereas the second DAC pulse is a return-to-zero (RZ)–type pulse; this is accomplished using a current-steering DAC. In order to reduce mismatch without using a data-weighted averaging circuit, the size and layout of the unit current source in the current-steering DAC are considered carefully. The CT-DSM achieves a signal-to-noise ratio (SNR) of 67.3 dB, a signal-to-noise and distortion ratio (SNDR) of 63.4 dB, and a dynamic range of 75 dB for a 20-MHz signal bandwidth.     

一种新型的高精度Sigma_Delta调制器结构

为实现低失真高动态范围的模数转换,提出了一种新型高精度Sigma_Delta调制器系统。首先,设计了一种新型的二阶单环一位量化结构,结构中增加两支前馈路径,并调整了核心积分器和信号加算模块的逻辑关系。同时,为实现量化噪声的二阶整形以及输入信号的无延迟传输,进一步适配和改进了积分器的传输函数。最终,所提出的调制器实现了更高的信噪比和更宽的动态输出范围。基于Matlab 的系统级仿真结果表明,在信号带宽1KHz、采样信号频率1024KHz的条件下,所提出调制器的信噪比为106.6dB,有效位数为17.41bit,二次谐波失真为-82.7dB,动态范围为104.76dB,整体指标性能良好,为高阶MASH结构Sigma Delta调制器的研发提供了新方向。     

A 13 bit 10 MHz bandwidth MASH 3–2 Σ∆ modulator in 90 nm CMOS

In this paper, a new multi loop sigma‐delta (ΣΔ) modulator is proposed which employs one order redundant noise shaping in the first stage so the effect of the quantization noise leakage is minimized. Thus, analog circuit requirements are considerably relaxed compared to the conventional Multi‐stAge‐noise‐SHaping (MASH) structures. This enhancement makes the structure appropriate for low voltage and broadband applications. The proposed architecture is compared with traditional high‐order structures, and the advantages are demonstrated by both the analysis and behavioral system level simulations. As a prototype, the proposed MASH 3–2 sigma‐delta modulator is designed, and the detailed design procedure is presented from the system level to the circuit level in a 90 nm CMOS technology. Circuit level simulation results show that the modulator achieves a peak signal‐to‐noise and distortion ratio of 79.4 dB and 79 dB dynamic range over a 10 MHz bandwidth with a sampling frequency of 160 MHz. It consumes 35.4 mW power from a single 1 V supply. Copyright © 2012 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

A 6th‐order 75 dB‐DR 10.7 MHz 3.3 V CMOS bandpass ΣΔ modulator sampled at 37.05 MHz

This paper describes the design and the implementation of a 6th‐order bandpass ΣΔ modulator to be used for IF digitizing at 10.7 MHz of a broadcasting FM radio signal. The modulator is sampled at 37.05 MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a standard double‐poly 0.35 µm CMOS technology using switched capacitor (SC) technique and consumes 116 mW from a single 3.3 V power supply. The modulator features 75 dB dynamic range and 66 dB peak‐SNR within a 200 kHz bandwidth (FM bandwidth). Third‐order intermodulation products are suppressed by –78dBc. Copyright © 2004 John Wiley & Sons, Ltd.     

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

In this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <?61‐dB IMD with 1.25‐GHz sampling frequency.     

A parasitic insensitive passive switched-capacitor interpolation finite impulse response filter

This paper proposes a passive switched-capacitor (SC) interpolation finite impulse response (IFIR) filter designed with complementary metal-oxide semiconductor (CMOS) 0.18-μm technology. Comparing with previous works in analog and digital domain, this filter consumes less power and takes advantage of passive SC circuits, providing high bandwidth and linearity. In addition, offset variation, which is distinctly observed in preceding works, and alteration in the pole, caused by output parasitic capacitance, are no longer present in the proposed filters. Also, a 15-tap IFIR filter with interpolation factor of 5 has been introduced in the paper, which is able to fully remove the effect of output parasitic capacitance. This filter, which is differentially designed, increases the sampling rate from 25 to 125 MHz and features P1dB and noise figure (NF) of −5 dBm and 20 dB, respectively. The result of process and temperature variation tests as well as Monte Carlo simulation performed for the circuit truly confirms the excellent performance of the filter. The highest image tone observed in the spectrum is below −57 dB, and the fixed pattern noise tone generated by charge injection, offset voltage, and its variation has been decreased to −65 dB. Moreover, the effect of clock feed through, capacitor mismatch, and clock phase mismatch as well as thorough and informative noise analysis has been presented for giving a better insight into nonidealities. This paper also analyzes the sensitivity of the position of notches to coefficient variation and enables optimization for reduced sensitivity.     

A 6‐bit 4 MS/s 26fJ/conversion‐step segmented SAR ADC with reduced switching energy for BLE

This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A UWB receiver with modified CS-CG LNTA: Noise and nonlinearity analysis

A modified common source-common gate (CS-CG) low-noise transconductance amplifier (LNTA) with an improved noise figure (NF), operational bandwidth, and power consumption are analyzed in this paper. The common source (CS) stage of the modified LNTA is utilized for noise cancellation and transconductance enhancement of the common gate (CG) transistor. Using these, NF, bandwidth, and power consumption are improved without using extra active elements. Noise analyses show the modified CS-CG LNTA has lower NF than conventional CS-CG LNTA. The linearity of the modified CS-CG LNTA is calculated by Taylor series expression. Besides, a design procedure is proposed based on the obtained equations for linearity and NF. Finally, an ultra-wideband (UWB) surface acoustic wave (SAW-less) direct-conversion receiver is designed in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. NF and third-order intercept point (IIP3) of the designed receiver are simulated as 5 dB and −2 dBm, respectively. The receiver consumes 18.4 mA from a 1.8 V supply voltage.     

An adaptive digital processor for power efficiency enhancement in hybrid supply modulators

A novel digital envelope modulator for envelope tracking radio frequency power amplifier is presented in this paper. The proposed modulator consists of a parallel combination of linear class AB and switching class D power amplifiers that are controlled digitally. In the previous analog architectures, the requirements needed for the AB operational amplifier such as high‐current driving capability, high bandwidth and large output swing is usually obtainable at high overall static power dissipation. The digitally controlled power opamp presented here not only provides the aforementioned requirements but also reduces power dissipation compared with previous work. Furthermore, the digital control of the modulator makes it adaptive to the input signal variations in comparison with conventional analog parallel hybrid envelope modulators. The digital processor of the modulator is evaluated with a 45‐nm complementary metal oxide semiconductor technology. The overall power consumption of the digital processor is around 142 mW at 1.5‐GHz clock frequency. As an application, the designed digital class AB is incorporated in a complete envelope modulator architecture. The overall efficiency of the modulator, including the digital processor power consumption, is around 82% at an average 32 dBm output power for a 5‐MHz input signal. Copyright © 2015 John Wiley & Sons, Ltd.     

Variation‐aware widely tunable nanoscale design of CMOS active inductor‐based RF bandpass filter

This paper presents a novel design methodology for realizing a variation‐aware widely tunable active inductor‐based RF bandpass filter (BPF). The inductor‐less filter is designed and implemented using voltage differencing transconductance amplifier (VDTA) as an active building block and a grounded capacitor, thereby validating its suitability for fully integrated circuit applications. Digital ‘coarse’ tuning and analog ‘fine’ tuning are employed to achieve better frequency coverage. The designed filter exhibits a tuning range of 1.65–3.015 GHz and a 3‐dB bandwidth of 1400–122 MHz which translates into a quality factor of 1.17–24.71. It offers a voltage gain of 0–22.91 dB, noise figure of 28.16–28.95 dB, has a 1‐dB compression point of 2.50–2.478 dBm and draws 0.065–0.232 mW power from 1‐V power supply. Our proposed design shows a figure‐of‐merit of 82.08–91.27 dB, which is higher as compared to its counterparts available in the literature. The filter is implemented in 45‐nm CMOS technology node using metal gate and strained silicon. Copyright © 2017 John Wiley & Sons, Ltd.     

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all-digital time-based quantization

Translating the analog input voltage to delay of delay cells is a necessity for realizing digital time-based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross-coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross-coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see-saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short-circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all-digital time-based analog to digital converter (ADC). The proposed 4-bit ADC, implemented in TSMC 65-nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm².     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.