Cascaded Multilevel Inverters Using Proposed Series Sub-multilevel Basic Blocks with Reduced Switching Devices

In this paper, a novel configuration of the cascaded multilevel inverters using series connection of new sub-multilevel basic blocks is presented. The basic structure of the proposed sub-multilevel inverter is made of three isolated batteries and eight unidirectional power switches. Hereby, by changing the polarity of one of such batteries and two power switches, two different modules of sub-multilevel inverters can be extracted that each of them is able to be incorporated into two different cascaded structures as the series basic blocks. Contemporary, to determine the suitable magnitudes of the integrated batteries, two different algorithms for each topology along with their relevant mathematical analysis have been also given. In this study, a complete comparison between the proposed topologies and several recently presented structures has been conducted. The compiled comparisons can prove the fact that both the proposed cascaded inverters are capable of generating a higher number of output voltage levels with less number of switching counts. Other advantages of these structures are reduction of voltage sources numbers, DC sources variety, value of total blocking voltage, and also conducting losses. In order to demonstrate the correct operation of the proposed structures and presented algorithms, some experimental results will be also shown.     

A New Cascaded Multi-level Inverter Topology with Reduced Number of Components and Charge Balance Control Methods Capabilities

In this article, a new basic unit for cascaded multi-level inverter is proposed. This inverter is able to increase the number of output voltage levels and reduces the number of power electronic devices. To generate all voltage levels at the output, five different algorithms to determine the magnitude of DC voltage sources are suggested. This inverter is compared with conventional cascaded multi-level inverters. The comparisons show that the proposed topology needs fewer DC voltage sources and power switches, less variety of the magnitude of DC voltage sources, and smaller amounts of blocked voltage by switches. As a result, the installation space and total cost of the inverter decrease. As it is impossible to use charge balance control methods for the asymmetric cascaded multi-level inverters, the developed topology based on the proposed cascaded inverter–the sub-symmetric topology with the usability of charge balance control methods–is proposed. A new algorithm is proposed to determine the magnitude of DC voltage sources. In addition, full-wave and half-wave charge balance control methods are applied in the proposed developed topology. The accurate performance of the proposed topology by applying charge balance control methods is verified through the simulation and experimental results of an 81-level sub-symmetric inverter.     

A new generalized switched diode multilevel inverter topology with reduced switch count and voltage on switches

This article presents a new multilevel inverter topology with reduced power switches. The proposed topology composes of several series connection of basic unit for obtaining a required output voltage level. The proposed topology can operate in symmetric condition. The proposed topology is connected in a cascaded structure to produce a higher number of output voltage levels. The proposed cascaded structure is optimized with the minimum number of components for the maximum number of levels. To prove the superiority of the proposed multilevel inverter topology, different technical parameter comparisons are carried out with recently developed multilevel inverter topologies from the literature. The calculation of total standing voltage is examined for the proposed topology. The operation of the proposed topology is tested and verified for nine-level output voltage. The simulated results are carried out, and it is strengthened by the real-time prototype results.     

Multilevel DC-link inverter

This paper presents a new class of multilevel inverters based on a multilevel dc link (MLDCL) and a bridge inverter to reduce the number of switches, clamping diodes, or capacitors. An MLDCL can be a diode-clamped phase leg, a flying-capacitor phase leg, or cascaded half-bridge cells with each cell having its own dc source. A multilevel voltage-source inverter can be formed by connecting one of the MLDCLs with a single-phase bridge inverter. The MLDCL provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, with or without pulsewidth modulation, to the bridge inverter, which in turn alternates the polarity to produce an ac voltage. Compared with the cascaded H-bridge, diode-clamped, and flying-capacitor multilevel inverters, the MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels m, the required number of active switches is 2/spl times/(m-1) for the existing multilevel inverters but is m+3 for the MLDCL inverters. Simulation and experimental results are included to verify the operating principles of the MLDCL inverters.     

FPGA控制的不对称多电平逆变器的设计

随着多电平技术在大容量场合的应用,不同结构的多电平拓扑结构不断被提出。论文研究一种混合级联式不对称多电平逆变器,该结构逆变器将传统H桥逆变器进行改进,与H桥相比使用相同器件时,该结构能够输出更多的电平数,或者在输出相同电平数的情况下比传统H桥级联结构使用更少的器件。该多电平逆变器由两个不对称四电平逆变器级联而成,输出电...     

Reduced common-mode modulation strategies for cascaded multilevel inverters

This paper presents modulation strategies for cascaded multilevel inverters that substantially eliminate common-mode voltage on the output phases. The paper begins by developing generic multilevel inverter reference waveforms that use only "allowed" space vectors to achieve reduced common-mode voltage. A graphical technique is then proposed that allows various carrier disposition modulation strategies for a diode-clamped inverter to be converted to equivalent modulation of a cascaded inverter for any fundamental reference waveform. This graphical technique is confirmed for both alternative phase opposition disposition and phase disposition equivalent modulation of a cascaded inverter, and is then used to create reduced common-mode modulation strategies for cascaded inverters from their equivalent counterparts for diode-clamped inverters under both continuous and discontinuous switching conditions. The strategies have been confirmed by both simulation and experimental results obtained using a cascaded five-level inverter.     

阶梯波调制级联逆变器触发角的一种简便算法

级联多电平逆变器除有效降低开关器件电压应力外,它还可以通过波形叠加改善输出波形的质量。阶梯波调制还可以减少开关次数、提高转换效率、降低EMI,是级联逆变器常用的一种工作模式。但目前国内外文献介绍的阶梯波调制的级联逆变器的触发角的计算方法存在计算复杂,而且只适用等电压差的问题,针对这种情况,本文提出了一种不同电压级差的阶梯波调制级联逆变器触发角的计算方法。该方法特别适用于太阳能电池级联逆变器、燃料电池级联逆变器的应用。此方法遵循等面积法原则,通过一定的约束条件,实现在线计算,利于工程实现,最后通过仿真验证了该方法的正确性。     

一种新型的H桥级联型逆变器空间矢量控制方法

将三电平空间矢量调制方法与传统的移相式SPWM方法相结合并应用于级联型结构,提出了一种新型的多电平移相型空间矢量控制方法.提出的空间矢量控制方法在软件和硬件实现上大大简化,很容易扩展到任意电平数,可以与矢量控制、直接转矩控制等相结合应用于电机调速系统.并在3单元级联型逆变器实验装置上进行了验证.仿真和实验都证明了这种方法的正确性与可行性.     

一种级联逆变器的分散式滤波器结构研究

本文研究了一种级联逆变器的分散式滤波器结构。和采用集中式滤波器时相比,采用分散式滤波器的级联逆变器不仅具有相同的输出特性,还可以更好地实现级联逆变器的模块化;同时,分散式滤波器结构对开关管的断路故障有较好的容错性,提高了级联系统的可靠性。本文以采用倍频载波相移SPWM调制的四通道级联逆变器为例,对比分析了采用集中式和分散式滤波器的级联逆变器的性能,仿真和实验验证了级联逆变器采用分散式滤波器的可行性。     

A reliable and efficient single-phase modular multilevel inverter topology

Bilevel inverters are replaced by multilevel inverters due to their capability of producing quality output voltage with low total harmonic distortion (THD). On the contrary, increase in number of semiconductor switches has questioned the reliability of the multilevel inverter topologies. To enhance the reliability, this paper proposes a single-phase five-level inverter topology with inherent fault-tolerant feature. The proposed inverter can sustain faults in sources and semiconductor switches by amending the switching combinations. No healthy switch is needed to be bypassed during the fault to ensure the optimum utilization of the switches. An analysis on the basis of reliability, cost, and efficiency is carried out of the proposed inverter and compared with the existing topologies. To prove the claim, the experimental results of the developed hardware model is analyzed and compared with the simulation results of MATLAB/SIMULINK.     

一种光伏发电用高增益多电平逆变器

针对传统的多电平逆变器存在有源器件数量较多、电容电压不平衡、结构复杂以及电压增益低的问题,提出一种降低器件数量且可扩展的多电平逆变器。该逆变器由开关电容单元和两个半桥组成,使用1个直流电源、3个电容、13个开关管,实现4倍电压增益和九电平交流输出电压。该逆变器通过2个半桥代替后端H桥转换输出电压极性,可以有效降低开关管总电压应力。在所提逆变器的扩展结构中,电容逐级充电的工作方式进一步提高了电压增益和输出电平数。首先,详细阐述了所提逆变器的工作模式、调制策略、电容分析、电压应力计算和电路参数设计。然后,与其他类似多电平逆变器进行了比较。最后,通过仿真与实验验证了所提逆变器的可行性和理论分析的正确性。     

Sinusoidal Pulse-width Modulated Three-phase Multi-level Inverter Topology

Abstract—This article presents a sinusoidal pulse-width modulated three-phase multi-level inverter topology. In this configuration, the basic two-level, three-phase inverter is modified to synthesize higher voltage levels by the insertion of two auxiliary switches per phase leg. The multi-level inverter configuration generates output voltage levels similar to the corresponding well-known conventional diode-clamped flying capacitors and cascaded H-bridge inverters but with fewer power circuit components and more simplicity. For output voltage and frequency variations demanded by such applications as variable-speed drives, active power filters, photovoltaic power conversions, etc., the sinusoidal pulse-width modulation technique is employed in the generation of the gating signals for the proposed three-phase multi-level inverter. A balanced three-phase R-L load is applied at the inverter output terminals, and the inverter performance is compared with that of other sinusoidal pulse-width modulated conventional multi-level inverter configurations. The validity of the proposed multi-level inverter topology and the modulation scheme are verified through simulations and experiments.     

Overdistention operation of cascaded multilevel inverters

In the past decade, the multilevel power converter has transitioned from an experimental concept to a standard product of many medium-voltage drive manufacturers. By utilizing small voltage steps, the multilevel topology offers higher power quality, higher voltage capability, lower switching losses, and improved electromagnetic compatibility over standard topologies. Recently, several researchers have focused on the cascaded multilevel inverter whereby two multilevel inverters are series connected to a motor load by splitting the neutral connection. The resulting performance is exceptional in terms of power quality since the overall number of voltage levels is effectively the product of the two cascaded inverters. This paper demonstrates that it is possible to extend this performance to an even higher number of voltage levels referred to as overdistended operation. This further improves the power quality that is significant in applications that have stringent total harmonic distorsion requirements, such as naval ship propulsion. A new control is introduced for overdistention operation and is validated with computer simulation and laboratory measurements.     

准Z源级联多电平光伏并网逆变器3次谐波补偿策略

光伏组件遮挡、老化等问题会使单相准Z源级联多电平逆变器单元间功率不平衡,严重时功率较大的单元会过调制,导致并网电流畸变甚至影响系统稳定。针对此问题,对单相准Z源级联多电平逆变器进行模型分析,阐述了过调制机理和最优3次谐波注入原理。在此基础上,提出一种优化的3次谐波补偿控制策略。该方法不仅能保证系统最大功率输出和单元间直流母线电压平衡,而且能根据拟合曲线选择出最优的3次谐波补偿系数,扩大逆变器运行范围,确保严重功率不平衡时所有单元都不过调制,抑制并网电流畸变效果明显。仿真和实验结果均验证了所提控制策略的有效性。     

一种非对称结构新型多电平逆变器及其控制策略

将电力电子基本单元这一概念加以推广,提出了一种新型非对称全桥电路拓扑;详细分析了这种多电平逆变器(Multi-level Inverter,简称MLI)的工作原理和换流模式.根据新型拓扑的特点,提出了具有针对性的SHEPWM控制算法;给出了预期的波形.进一步对单相和三相逆变电路的系统进行了仿真;验证了特定谐波消除的正确性,并证明了单相m电平逆变器组合成三相后,线电压总共有2m-1个电平这一理论.     

一种混合级联型多电平逆变器拓扑结构

在交流电动机调速领域,大容量多电平变换器的应用越来越广泛,为了改善系统性能,各种各样的多电平拓扑结构被提出.本文提出了一种新颖的混合级联式多电平拓扑结构,该结构将传统的H桥逆变器(主逆变器)和二极管钳位型三电平逆变器(从逆变器)结合起来,串联为电动机供电,而这其中仅仅只有主逆变器需要电压源.这种新型的拓扑结构由于增加了从逆变器作为辅助单元用于能量存储,可以提高系统的效率,一定程度上实现电动机的四象限运行.相比传统的H桥逆变器,该拓扑可以减少输入电压源的数目;当电动机以稳定速度运行时,从逆变器可以为负载提供无功能量.该拓扑结构在电力机车和大型舰船推进系统等领域有着广泛的应用前景.     

一种新型的无变压器级联型多电平变换器拓扑

H桥级联多电平逆变器在高压大容量变频调速领域得到了广泛的应用,其最大的不足之处是必须使用庞大、复杂而昂贵的多绕组移相隔离变压器。为了省去传统H桥级联多电平变换器中的多绕组移相变压器,提出了一种新型的无变压器级联型多电平变换器拓扑结构。该拓扑由通用拓扑结构派生而来,全部由基本单元级联而成,不需要大量独立直流电源,省去了多绕组移相隔离变压器,具有模块性强、结构简单、易于扩展等优点。和现有的主要多电平拓扑结构相比,随着电平数的增多,使用元件较少,更适合于五电平及以上多电平使用。以五电平拓扑为例进行了研究,分析了其工作原理和悬浮电容电压平衡控制方法,仿真和实验结果验证了其可行性。     

DC–AC Cascaded H-Bridge Multilevel Boost Inverter With No Inductors for Electric/Hybrid Electric Vehicle Applications

This paper presents a cascaded H-bridge multilevel boost inverter for electric vehicle (EV) and hybrid EV (HEV) applications implemented without the use of inductors. Currently available power inverter systems for HEVs use a dc–dc boost converter to boost the battery voltage for a traditional three-phase inverter. The present HEV traction drive inverters have low power density, are expensive, and have low efficiency because they need a bulky inductor. A cascaded H-bridge multilevel boost inverter design for EV and HEV applications implemented without the use of inductors is proposed in this paper. Traditionally, each H-bridge needs a dc power supply. The proposed design uses a standard three-leg inverter (one leg for each phase) and an H-bridge in series with each inverter leg which uses a capacitor as the dc power source. A fundamental switching scheme is used to do modulation control and to produce a five-level phase voltage. Experiments show that the proposed dc–ac cascaded H-bridge multilevel boost inverter can output a boosted ac voltage without the use of inductors.      

Cascaded Common Nodal Point Multi-level Inverter Topology

Recent trends in the multi-level inverter (MLI) technology demand reduced number of switches, driver circuits, isolated DC sources, peak inverse voltage (PIV), appreciable number of voltage level, and lower total harmonic distortion. This paper presents an improved cascaded MLI configuration. Each module comprises ten switches, two isolated DC sources, and two capacitors; it can generate a maximum of 9-level output voltage waveform. Optimized switching sequence is developed that ensures minimum switching transitions and is implemented through single-carrier pulse width modulation for the control of the proposed topology. The classical cascaded H-bridge inverter and some recently developed MLI configurations were compared with the proposed inverter circuit. Results show that the proposed inverter configuration generates high number of output voltage levels with reduced number of power switches and PIV. It also has a lower per-unit power loss profile. Unit capacitor voltage balancing scheme is developed, which ensures proper control of the unit step voltage level in each of the cascaded modules, at extreme loading condition. For two cascaded inverter modules, simulation and experimental verifications are carried out on the proposed inverter for an R–L load. Simulation results of the output voltage waveforms and its harmonic spectrum are in conformity with experimental results.     

A bidirectional diode containing multilevel inverter topology with reduced switch count and driver

In this paper, a bidirectional diode containing multilevel inverter is introduced to reduce the number of switching elements especially in the case of a high number of output voltage levels. In comparison with classic and recently introduced symmetrical topologies, which are trying to reduce the switch count, this topology has a lower number of semiconductor switches in the same number of output voltage levels. This makes the proposed inverter to be a suitable choice for medium voltage applications like renewable energy applications as well as medium voltage electric drives. Moreover, it can be used in a cascaded configuration for high voltage levels. To depict the performance of the proposed structure, a comprehensive comparison is made between this topology and classic and recently proposed symmetric topologies in terms of switch and gate driver count, power losses, and cost. The performance of the proposed symmetrical 11-level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable but also the experimental results of laboratory prototype validate the simulation results.