Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

In this paper, an analytical short-channel threshold voltage model is presented for double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs. The threshold voltage model is based on the “virtual cathode” concept which is determined by the two-dimensional (2D) channel potential of the device. The channel potential has been determined by solving 2D Poisson’s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si_1?x Ge _x layer. The effects of various device parameters like Ge mole fraction, Si film thickness, SiGe thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been estimated. The validity of the present 2D analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.     

Si IGBT/SiC MOSFET混合器件及其应用研究

综述了Si IGBT/SiC MOSFET混合器件在门极优化控制策略、集成驱动设计、热电耦合损耗模型、芯片尺寸配比优化和混合功率模块研制等方面的最新研究成果与进展。Si IGBT/SiC MOSFET混合器件结合了SiC MOSFET的高开关频率、低开关损耗特性和Si IGBT的大载流能力和低成本优势,已有文献的最新研究和实验结果验证了该类器件的优异特性,表明其对高性能电力电子器件实现更高电流容量、更高开关频率和较低成本具有重要意义,是高性能变换器应用中非常有潜力的功率器件类型。     

Compact modeling and simulation of nanoscale fully depleted DG-SOI MOSFETS

A two dimensional analytical model for nanoscale fully depleted double gate SOI MOSFET is presented. Green??s function solution technique is adopted to solve the two dimensional Poisson??s equation using Dirichlet??s and Neumann??s boundary conditions at silicon-silicon di-oxide interface. Based on the derived 2D potential distribution, surface potential distributions in the Si film are analytically obtained. The calculated minimum surface potential is used to develop an analytic threshold voltage model. Simulation is done using ATLAS simulator for a 65?nm device and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data and other published results.     

The push toward low voltage devices

Since the early 1980s, increasing attention has been focused on the development and manufacture of low voltage and low power electronics. The motivation for this trend is multifaceted. For RF and microwave circuitry, the constraints implied by the low voltage imperative can be examined as they apply to every aspect of RF/microwave component development. The ultimate success of a low voltage and low power RF product strategy is affected by all of the following issues: materials technology (GaAs, Si, epitaxy, implant, heterojunctions); device technology (BJT, HBT, MESFET, MOSFET, HEMT); circuit technology (topology challenges for low voltage); and radio system design issues (architecture trends and low voltage). Of these factors, system architecture has the greatest potential impact     

考虑器件工作温度影响的Si C功率MOSFET建模

提出一种基于MATLAB/Simulink的SiC功率MOSFET全工作区变温度参数建模方法。在Si基横向双扩散MOSFET模型的基础上,采用与温度相关的电流源和电压源补偿器件漏极电流和阈值电压的变化。通过补充实验拓展SiC功率MOSFET的饱和区工作特性曲线,并根据Si C功率MOSFET的工作特性,采用数学拟合的方法来提取模型参数。在保留各个参数物理意义的同时,摆脱建模过程对物理参数的依赖。在不同电压、电流及温度(25~200℃)的情况下对器件的输出特性、转移特性、阈值电压、导通电阻及开关损耗进行测试,将测试结果与MATLAB/Simulink模型仿真结果进行性比较。模型仿真结果与实际测试结果一致,开关损耗误差在7%之内,验证了模型的准确性及有效性,为实际应用Si C功率MOSFET时系统性能及损耗分析提供参考依据。     

Germanium: The semiconductor comeback material

In this paper, Ge the comeback semiconductor material is discussed. It is used as an enabling material for the next generation of device technology primarily due to its high carrier mobility. Ge, along with other high-mobility such as III/V compounds, are projected to be the the new range of semiconductor material. The technology for the growth of Ge and (In) GaAs active areas on an Si substrate must be developed     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.